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| author | John Su <john_su@compal.corp-partner.google.com> | 2025-04-23 10:34:37 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2025-04-26 13:44:08 +0000 |
| commit | 54c87dbed07d8060f5e89391ae6ef32f87dfe5c5 (patch) | |
| tree | 9225815e6832cd4748675c9d9bc67dcc0250347d | |
| parent | 9ef62ad64c2fe3373da1ee0fc7dfe91d9169f207 (diff) | |
| download | coreboot-main.tar.gz coreboot-main.tar.bz2 coreboot-main.zip | |
Update the DPTF parameters as provided by thermal team.
1. Tcc_offset: 5 -> 3
2. Modify critical policy and passive policy setting
BUG=b:411866724
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team
Change-Id: Id5fda2e8c4985d41d0871454bb808a9cdfedc3e6
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87425
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/uldrenite/overridetree.cb | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 55e15175c745..78fec3dab2b2 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -30,7 +30,7 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "true" - register "tcc_offset" = "5" # TCC of 100 + register "tcc_offset" = "3" # Enable CNVi BT register "cnvi_bt_core" = "true" @@ -194,17 +194,17 @@ chip soc/intel/alderlake ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 5000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 98, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 98, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 98, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 130, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 105, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN), }" register "controls.power_limits" = "{ @@ -213,14 +213,14 @@ chip soc/intel/alderlake .max_power = 10000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC, - .granularity = 500 + .granularity = 125 }, .pl2 = { .min_power = 25000, .max_power = 25000, - .time_window_min = 32 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 500 + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 1000 } }" |