diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2023-10-21 20:24:22 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-23 20:58:15 +0000 |
| commit | 80b5fe69f6d9897173d0fa7c0284be678d775821 (patch) | |
| tree | cb0d81d8b26c055e87d86a12597aa62b4242e16f | |
| parent | f5f1ff355e4e114988f8f66c7969336527a7c915 (diff) | |
| download | coreboot-80b5fe69f6d9897173d0fa7c0284be678d775821.tar.gz coreboot-80b5fe69f6d9897173d0fa7c0284be678d775821.tar.bz2 coreboot-80b5fe69f6d9897173d0fa7c0284be678d775821.zip | |
soc/intel/common/pcie: Disable removed RPs when updating devicetree
If a root port is not present but was enabled in the devicetree, mark
it disabled so that no ACPI references will be generated by any
function which walks the devicetree (eg, LPI constraints).
TEST=tested with rest of patch train
Change-Id: I52e23fb1c0148a599ed736fc294e593ebbd27860
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78517
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/common/block/pcie/pcie_rp.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 145159f6eb66..650da1ff9149 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -115,8 +115,9 @@ static bool pcie_rp_update_dev( if (new_fn < 0) { if (dev->enabled) { printk(BIOS_NOTICE, "%s: Couldn't find PCIe Root Port #%u " - "(originally %s) which was enabled in devicetree, removing.\n", + "(originally %s) which was enabled in devicetree, removing and disabling.\n", __func__, rp_idx + 1, dev_path(dev)); + dev->enabled = 0; } return true; } else if (PCI_FUNC(dev->path.pci.devfn) != new_fn) { |