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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-01-04 20:09:27 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-01-04 20:09:27 +0000
commit1f807fd42f4c4d175c2af1357979fdf235f0be9a (patch)
tree4cb7b0ab245a5b14e1e15ff59ffa51e849a47f70
parentce56835a5cc2cb762ecba0d672a9d33fbfc2f7fd (diff)
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- Fix UDELAY options and HAVE_INIT_TIMER [kconfig]
(defaults to UDELAY_IO again, like newconfig) - Use UDELAY_TSC on Via C7 [kconfig] - Support Tinybootblock on Intel CPUs - set XIP location correctly for Tinybootblock on Intel - provide correct XIP location in Tinybootblock configuration - Make kontron/986lcd-m use Tinybootblock - Some kconfig fixes to kontron/986lcd-m [kconfig] Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat
-rw-r--r--src/Kconfig1
-rw-r--r--src/arch/i386/Makefile.tinybootblock.inc4
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc8
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram_disable.c2
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc8
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram_disable.c2
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram.inc8
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram_disable.c2
-rw-r--r--src/cpu/via/model_c7/Kconfig1
-rw-r--r--src/cpu/x86/Kconfig1
-rw-r--r--src/mainboard/kontron/986lcd-m/Kconfig7
-rw-r--r--src/mainboard/kontron/986lcd-m/Makefile.inc8
12 files changed, 34 insertions, 18 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 6fe473c5993f..20a1a13f6b2c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -186,6 +186,7 @@ config HAVE_HARD_RESET
config HAVE_INIT_TIMER
bool
+ default n if UDELAY_IO
default y
config HAVE_MAINBOARD_RESOURCES
diff --git a/src/arch/i386/Makefile.tinybootblock.inc b/src/arch/i386/Makefile.tinybootblock.inc
index a3f38ce0716b..4aa6a84740c5 100644
--- a/src/arch/i386/Makefile.tinybootblock.inc
+++ b/src/arch/i386/Makefile.tinybootblock.inc
@@ -67,13 +67,13 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl
# Build the romstage
$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $(initobjs) $(obj)/romstage/ldscript.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
- printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
+ printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
$(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
cat $(obj)/location.txt >> $(obj)/location.ld
- printf ";\n" >> $(obj)/location.ld
+ printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
$(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
$(OBJCOPY) -O binary $(obj)/romstage.elf $@
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index a216aa3295fc..dec09fee6576 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -114,7 +114,13 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
index 7808d56f31bf..d52bf0b17818 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
@@ -25,6 +25,7 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -46,6 +47,7 @@ void stage1_main(unsigned long bist)
);
fallback_image:
#endif
+#endif
real_main(bist);
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 9623dc4086ff..28d510066d41 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -104,7 +104,13 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
index a22978e05177..fcdd3f2e1987 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
@@ -27,6 +27,7 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@ void stage1_main(unsigned long bist)
);
fallback_image:
#endif
+#endif
real_main(bist);
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 5082a2e4dbb5..a664da2f8736 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -111,7 +111,13 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
index a22978e05177..fcdd3f2e1987 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
@@ -27,6 +27,7 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@ void stage1_main(unsigned long bist)
);
fallback_image:
#endif
+#endif
real_main(bist);
diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig
index 22daaf434fe2..8a2fe88a442a 100644
--- a/src/cpu/via/model_c7/Kconfig
+++ b/src/cpu/via/model_c7/Kconfig
@@ -1,2 +1,3 @@
config CPU_VIA_C7
bool
+ select UDELAY_TSC
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index a3b9330e64e1..59f27de7940b 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -8,6 +8,7 @@ config WAIT_BEFORE_CPUS_INIT
config UDELAY_IO
bool
+ default y if !UDELAY_LAPIC && !UDELAY_TSC
default n
config UDELAY_LAPIC
diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig
index 3fe873793f7e..983232fca0d5 100644
--- a/src/mainboard/kontron/986lcd-m/Kconfig
+++ b/src/mainboard/kontron/986lcd-m/Kconfig
@@ -21,7 +21,7 @@ config BOARD_KONTRON_986LCD_M
select IOAPIC
select USE_DCACHE_RAM
select GFXUMA
- select HAVE_MOVNTI
+ select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
@@ -72,8 +72,3 @@ config FALLBACK_VGA_BIOS_FILE
string
default "amipci_01.20"
depends on BOARD_KONTRON_986LCD_M
-
-config HAVE_ACPI_SLIC
- bool
- default n
- depends on BOARD_KONTRON_986LCD_M
diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc
index 5cd84bcde7d5..d0c2883a6e59 100644
--- a/src/mainboard/kontron/986lcd-m/Makefile.inc
+++ b/src/mainboard/kontron/986lcd-m/Makefile.inc
@@ -40,18 +40,12 @@ smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
initobj-y += crt0.o
# FIXME in $(top)/Makefile
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
ifdef POST_EVALUATION
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-13 07:27:24 +0000