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| author | Matt DeVillier <matt.devillier@gmail.com> | 2019-08-24 23:54:41 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-30 10:42:57 +0000 |
| commit | f672d50e2bad1d35e820ab32b76dbf95a7b90a35 (patch) | |
| tree | 8e6c7a7e57e68b80ba7f91b924ab0e9013e99efa | |
| parent | ae317695e3f03d55fbba1805ff06e004383e67c8 (diff) | |
| download | coreboot-f672d50e2bad1d35e820ab32b76dbf95a7b90a35.tar.gz coreboot-f672d50e2bad1d35e820ab32b76dbf95a7b90a35.tar.bz2 coreboot-f672d50e2bad1d35e820ab32b76dbf95a7b90a35.zip | |
google/link: fix detection of dimm on channel 1
Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.
Test: boot google/link, observe onboard RAM correctly
detected on both channels
Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
(cherry picked from commit 4af1fe23f8658ec51380b68ecdd317ddc1dfb854)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35046
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/mainboard/google/link/romstage.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f3f07cdce5e..8e8d94335c53 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -156,8 +156,12 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(pei_data->spd_data[0], locate_spd(), sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[2], pei_data->spd_data[0], + sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -180,7 +184,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(&spd[0], locate_spd(), 128); + memcpy(&spd[2], &spd[0], 128); } void mainboard_early_init(int s3resume) |