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authorNico Huber <nico.h@gmx.de>2019-11-17 01:35:14 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:50:47 +0000
commit052e3ef3345b0281de7a0f751ab6d3fd1b4d6932 (patch)
tree7730589628e52b02287abf97f8f423e35ee0fc5b
parent9f2eca50eaeb8a1b2d53867e8659d889f5ac5ad5 (diff)
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mb/intel/emeraldlake2: Revise early init
Move UART initialization to bootblock_mainboard_early_init() and don't override the generic LPC decode settings. Change-Id: Icdab36ae0324175d3d51a050784b94a53d4b3b7c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/mainboard/intel/emeraldlake2/early_init.c17
1 files changed, 2 insertions, 15 deletions
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 94a46550b211..7aabf7c1ec7c 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -29,26 +29,13 @@
#define SIO_PORT 0x164e
-void mainboard_pch_lpc_setup(void)
-{
- pci_devfn_t dev = PCH_LPC_DEV;
-
- /* Enable SuperIO + PS/2 Keyboard/Mouse */
- u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
- pci_write_config16(dev, LPC_EN, lpc_config);
-
- /* Enable COM1 */
- if (sio1007_enable_uart_at(SIO_PORT)) {
- pci_write_config16(dev, LPC_EN,
- lpc_config | COMA_LPC_EN);
- }
-}
-
void bootblock_mainboard_early_init(void)
{
const u16 port = SIO_PORT;
const u16 runtime_port = 0x180;
+ sio1007_enable_uart_at(port);
+
/* Turn on configuration mode. */
outb(0x55, port);