sb/intel/bd82x6x: Make the pch_enable_lpc hook optional

This also changes the name to mainboard_pch_lpc_setup to better
reflect that it is an optional mainboard hook.

This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.

Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

47 files changed, 31 insertions, 109 deletions

diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c
index 5522ea013e52..f445eea28e7d 100644
--- a/src/mainboard/apple/macbookair4_2/romstage.c
+++ b/src/mainboard/apple/macbookair4_2/romstage.c
@@ -20,7 +20,7 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <cbfs.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c
index fe1416b908d7..983de07ff716 100644
--- a/src/mainboard/asrock/b75pro3-m/romstage.c
+++ b/src/mainboard/asrock/b75pro3-m/romstage.c
@@ -23,10 +23,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },
diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c
index 4c8eda74fef6..2aa243f4e859 100644
--- a/src/mainboard/asus/h61m-cs/romstage.c
+++ b/src/mainboard/asus/h61m-cs/romstage.c
@@ -27,10 +27,6 @@
 #define SIO_DEV		PNP_DEV(SIO_PORT, 0)
 #define ACPI_DEV	PNP_DEV(SIO_PORT, NCT6779D_ACPI)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },
diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c
index e29dd0f160e3..c1e397529468 100644
--- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c
+++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c
@@ -40,10 +40,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c
index 01ae6030ad48..d3361919a7a4 100644
--- a/src/mainboard/asus/p8h61-m_lx/romstage.c
+++ b/src/mainboard/asus/p8h61-m_lx/romstage.c
@@ -41,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_or_config16(PCH_LPC_DEV, LPC_EN,
 			CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c
index 3736ab6b6584..ff5a67748d90 100644
--- a/src/mainboard/asus/p8h61-m_pro/romstage.c
+++ b/src/mainboard/asus/p8h61-m_pro/romstage.c
@@ -25,7 +25,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
 #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Enable the Super IO */
 	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN |
diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c
index 5fff2e143c36..4963c3102ce9 100644
--- a/src/mainboard/asus/p8z77-m_pro/romstage.c
+++ b/src/mainboard/asus/p8z77-m_pro/romstage.c
@@ -30,10 +30,6 @@
 #define GLOBAL_DEV PNP_DEV(0x2e, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* {enable, current, oc_pin} */
 	{ 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index f44a7e8edd3f..4176703ac7b3 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -22,7 +22,7 @@
 
 #define SIO_PORT 0x164e
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_devfn_t dev = PCH_LPC_DEV;
 
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 25e1d0385ea9..a5d4c35b34c0 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -25,7 +25,7 @@
 #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
 #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
index 57cc0706d94b..a68070fbe6bd 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -23,10 +23,6 @@
 #define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO)
 #define SERIAL_DEV PNP_DEV(0x2e, 0x01)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 3aef9d0a09b9..e1d948d89fad 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -28,7 +28,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* EC Decode Range Port60/64 and Port62/66 */
 	/* Enable EC and PS/2 Keyboard/Mouse*/
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 628e2a00526a..3fd90e9b17cd 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -32,7 +32,7 @@
 
 #include <southbridge/intel/bd82x6x/chip.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
 	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 604cf7b284c3..caff3f5436ad 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -26,10 +26,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include "ec/compal/ene932/ec.h"
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_late_rcba_config(void)
 {
 	u32 reg32;
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index cbbae2ee0792..d8e04eaa6356 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -30,7 +30,7 @@
 #include "ec.h"
 #include "onboard.h"
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/*
 	 * Enable:
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c
index 8d36f6b27def..f1d1e905f304 100644
--- a/src/mainboard/hp/2570p/romstage.c
+++ b/src/mainboard/hp/2570p/romstage.c
@@ -20,10 +20,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 0, 1, 0 },
diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
index 5bf878961801..acf5b1895a57 100644
--- a/src/mainboard/hp/2760p/romstage.c
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -19,10 +19,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 1, 0 },
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
index 397810eba7e8..4e4b17536629 100644
--- a/src/mainboard/hp/8460p/romstage.c
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -23,10 +23,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* USB0, eSATA */
 	{ 1, 0, 0 }, /* USB charger */
diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c
index 513b3756e860..8c9b29ef01c7 100644
--- a/src/mainboard/hp/8470p/romstage.c
+++ b/src/mainboard/hp/8470p/romstage.c
@@ -22,10 +22,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 1, 0 },
diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c
index d3034fb5650a..8eefe4d6a287 100644
--- a/src/mainboard/hp/8770w/romstage.c
+++ b/src/mainboard/hp/8770w/romstage.c
@@ -23,10 +23,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* Dock USB3.0 */
 	{ 1, 1, 0 }, /* Conn */
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
index 3e726cfb808c..df581fe542f0 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
+++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
@@ -27,10 +27,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 	{ 1, 0, -1 },
diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c
index 969b666d8fd7..07ee1eb2832c 100644
--- a/src/mainboard/hp/folio_9470m/romstage.c
+++ b/src/mainboard/hp/folio_9470m/romstage.c
@@ -21,10 +21,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* SSP1: dock */
 	{ 1, 1, 0 }, /* SSP2: left, EHCI Debug */
diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c
index 844bb2f4e353..24247420ab3b 100644
--- a/src/mainboard/hp/revolve_810_g1/romstage.c
+++ b/src/mainboard/hp/revolve_810_g1/romstage.c
@@ -24,10 +24,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_late_rcba_config(void)
 {
 	RCBA32(BUC) = 0x00000000;
diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c
index 2e0a50806c97..0b9ffe4d5637 100644
--- a/src/mainboard/hp/z220_sff_workstation/romstage.c
+++ b/src/mainboard/hp/z220_sff_workstation/romstage.c
@@ -27,10 +27,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 1cd58b0ba5df..8f382703881c 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -27,10 +27,6 @@
 #include "superio.h"
 #include "thermal.h"
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_late_rcba_config(void)
 {
 	/* Disable devices */
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 16a16de33f88..2cfb5569fb52 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -28,7 +28,7 @@
 
 #define SIO_PORT 0x164e
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_devfn_t dev = PCH_LPC_DEV;
 
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 37713e1657b7..3b49653f972f 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -27,7 +27,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <superio/winbond/common/winbond.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070);
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index 37182f855d56..af73537f2432 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -22,10 +22,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 	{ 1, 0, -1 },
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index ee1d0ed19ccc..055217066819 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -27,7 +27,7 @@
 
 #define SPD_LEN 256
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index 7036ec40fe9b..e04803f16541 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -49,7 +49,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 7b97ff7e75bd..764997297e02 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -49,7 +49,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
index 0cff5d2b59b7..f1e724be471b 100644
--- a/src/mainboard/lenovo/t430/romstage.c
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -49,10 +49,6 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
-{
-}
-
 /* FIXME: used T530 values here */
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 },
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index 298673b5dd9f..6503c9a92088 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -19,7 +19,7 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 52898faa4524..caf54bd5dfac 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -51,7 +51,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index e0b0455c757b..85c3090bb5d4 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -51,7 +51,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c
index a1d3e88ad71c..45d6b8809956 100644
--- a/src/mainboard/lenovo/x131e/romstage.c
+++ b/src/mainboard/lenovo/x131e/romstage.c
@@ -20,10 +20,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{1, 1, 0},	/* P0: USB 3.0 1 (OC0) */
 	{1, 1, 0},	/* P1: USB 3.0 2 (OC0) */
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index f4d2a3c70aa2..1f027ffab8cc 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -28,7 +28,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <cbfs.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 7989fd6298ef..72dd8dddcab2 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -27,7 +27,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <cpu/x86/msr.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 3e9ea2c3717c..56f5a90670d7 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -24,7 +24,7 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c
index 399d44b2a47b..1dd3fd06a856 100644
--- a/src/mainboard/msi/ms7707/romstage.c
+++ b/src/mainboard/msi/ms7707/romstage.c
@@ -20,7 +20,7 @@
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	u16 reg16;
 	reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);
diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c
index 4491370cbf73..38c406477287 100644
--- a/src/mainboard/roda/rv11/variants/rv11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c
@@ -21,10 +21,6 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c
index f355578b6e6e..7321dac39852 100644
--- a/src/mainboard/roda/rv11/variants/rw11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c
@@ -25,10 +25,6 @@
 #include <superio/ite/it8783ef/it8783ef.h>
 #include <superio/ite/common/ite.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO);
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index ddcf2ad9e6fc..d6ded7a5596c 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -33,7 +33,7 @@
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Set COM1/COM2 decode range */
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 06659978e597..35dc055baa58 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -45,7 +45,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Set COM1/COM2 decode range */
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
index 3c9cc829d759..bc08fd8bf2de 100644
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -21,7 +21,7 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
 }
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index d667e365715f..cfda2e838b57 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -212,7 +212,6 @@ void sandybridge_late_initialization(void);
 void northbridge_romstage_finalize(int s3resume);
 void early_init_dmi(void);
 
-void pch_enable_lpc(void);
 /* mainboard_early_init: Optional mainboard callback run after console init
    but before raminit. */
 void mainboard_early_init(int s3resume);
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index d8fd7ad6a5c5..8ffb22e14029 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -286,12 +286,16 @@ static void pch_enable_lpc_decode(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 }
 
+__weak void mainboard_pch_lpc_setup(void)
+{
+}
+
 void early_pch_init(void)
 {
 
 	pch_enable_lpc_decode();
 
-	pch_enable_lpc();
+	mainboard_pch_lpc_setup();
 
 	pch_enable_bars();
 
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index d4cd86eaa518..127fb61cce44 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -75,6 +75,9 @@ void southbridge_rcba_config(void);
 /* Optional mainboard hook to do additional configuration
    on the RCBA config space. It is called after the raminit. */
 void mainboard_late_rcba_config(void);
+/* Optional mainboard hook to do additional LPC configuration
+   or to override what is set up by default. */
+void mainboard_pch_lpc_setup(void);
 void early_pch_init_native(void);
 void early_pch_init(void);
 void early_pch_init_native_dmi_pre(void);