intel/broadwell: Implement proper backlight PWM config

Port the backlight-PWM handling from Skylake instead of the previously
used Haswell version. We use a 200Hz PWM signal for all boards. Which
is higher than the previous devicetree value, 183Hz, but that was over-
ridden by the VBIOS anyway. 200Hz is still very low, considering LED
backlights, but accurate values are unknown at this time.

Lynx Point, the PCH for Haswell and Broadwell, is a transition point
for the backlight-PWM config. On platforms with a PCH, we have:

  o Before Lynx Point:
    The CPU has no PWM pin and sends the PWM duty-cycle setting
    to the PCH. The PCH can choose to ignore that and use its own
    setting (BLM_PCH_OVERRIDE_ENABLE).
    We use the CPU setting on these platforms.
  o Lynx Point + Haswell:
    The CPU has an additional PWM pin but can be set up to send
    its setting to the PCH as before. The PCH can still choose
    to ignore that.
    We use the CPU setting with Haswell.
  o Lynx Point + Broadwell:
    The CPU can't send its setting to the PCH anymore. BLM_PCH_
    OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is
    used (it virtually always is).
    We have to use the PCH setting in this case.
  o After Lynx Point:
    Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is
    implied and the bit not implemented anymore.

Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

10 files changed, 49 insertions, 34 deletions

diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
index b31d82979c21..f6ec15a61714 100644
--- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
@@ -9,9 +9,8 @@ chip soc/intel/broadwell
 	# Enable HDMI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000000"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
index 3c00ec954fc5..db02565b278e 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
@@ -9,9 +9,8 @@ chip soc/intel/broadwell
 	# Enable HDMI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000000"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb
index f75da84eee8c..e12882f413fe 100644
--- a/src/mainboard/google/auron/variants/buddy/devicetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb
@@ -9,9 +9,8 @@ chip soc/intel/broadwell
 	# Enable HDMI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000000"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb
index 118e646ee08d..230f5bd00915 100644
--- a/src/mainboard/google/auron/variants/gandof/devicetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb
@@ -9,9 +9,8 @@ chip soc/intel/broadwell
 	# Enable HDMI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000000"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb
index 622ea3488de3..1983045983ab 100644
--- a/src/mainboard/google/auron/variants/lulu/devicetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb
@@ -9,9 +9,8 @@ chip soc/intel/broadwell
 	# Enable HDMI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000000"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb
index a6c2feae5652..434ecc80b9c0 100644
--- a/src/mainboard/google/auron/variants/samus/devicetree.cb
+++ b/src/mainboard/google/auron/variants/samus/devicetree.cb
@@ -9,9 +9,8 @@ chip soc/intel/broadwell
 	# Enable DDI2 Hotplug with 6ms pulse
 	register "gpu_dp_c_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000200"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb
index e713cd2f5602..98b5163b5f8b 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb
@@ -6,9 +6,8 @@ chip soc/intel/broadwell
 	# Enable DDI1 Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000200"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb
index 3e83d3fb1a06..32c3ed166f76 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb
@@ -6,9 +6,8 @@ chip soc/intel/broadwell
 	# Enable DDI1 Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000200"
+	# Set backlight PWM value for eDP
+	register "gpu_pch_backlight_pwm_hz" = "200"
 
 	# Enable Panel and configure power delays
 	register "gpu_panel_port_select" = "1"			# eDP
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 456a4354ca8c..18a65857a739 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -117,8 +117,11 @@ struct soc_intel_broadwell_config {
 	u16 gpu_panel_power_backlight_off_delay;
 
 	/* Panel backlight settings */
-	u32 gpu_cpu_backlight;
-	u32 gpu_pch_backlight;
+	unsigned int gpu_pch_backlight_pwm_hz;
+	enum {
+		GPU_BACKLIGHT_POLARITY_HIGH = 0,
+		GPU_BACKLIGHT_POLARITY_LOW,
+	} gpu_pch_backlight_polarity;
 
 	/*
 	 * Graphics CD Clock Frequency
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index dab2d1575014..f4322bf70e9d 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -335,14 +335,34 @@ static void igd_setup_panel(struct device *dev)
 		gtt_write(PCH_PP_DIVISOR, reg32);
 	}
 
-	/* Enable Backlight if needed */
-	if (conf->gpu_cpu_backlight) {
-		gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
-		gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight);
-	}
-	if (conf->gpu_pch_backlight) {
-		gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
-		gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight);
+	/* So far all devices seem to use the PCH PWM function.
+	   The CPU PWM registers are all zero after reset.      */
+	if (conf->gpu_pch_backlight_pwm_hz) {
+		/* For Lynx Point-LP:
+		   Reference clock is 24MHz. We can choose either a 16
+		   or a 128 step increment. Use 16 if we would have less
+		   than 100 steps otherwise. */
+		const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
+		unsigned int pwm_increment, pwm_period;
+		u32 south_chicken2;
+
+		south_chicken2 = gtt_read(SOUTH_CHICKEN2);
+		if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
+			pwm_increment = 16;
+			south_chicken2 &= ~(1 << 5);
+		} else {
+			pwm_increment = 128;
+			south_chicken2 |= 1 << 5;
+		}
+		gtt_write(SOUTH_CHICKEN2, south_chicken2);
+
+		pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
+		/* Start with a 50% duty cycle. */
+		gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
+
+		gtt_write(BLC_PWM_PCH_CTL1,
+			(conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
+			BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
 	}
 }