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| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-05-24 11:16:30 -0600 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-09 04:09:14 +0000 |
| commit | 463aee755ed1ac94c8c433fcfad6302cf37f22fb (patch) | |
| tree | a0dc5d0bf70f6e8f4ec81f1a56467f5d459e517b | |
| parent | 4a3e7dd31d090272d2b11bb8c48aa8bad09a3760 (diff) | |
| download | coreboot-463aee755ed1ac94c8c433fcfad6302cf37f22fb.tar.gz coreboot-463aee755ed1ac94c8c433fcfad6302cf37f22fb.tar.bz2 coreboot-463aee755ed1ac94c8c433fcfad6302cf37f22fb.zip | |
mainboard/ocp/monolake: Clean up devicetree.cb
Clean up the device tree as noted by the coreboot log.
PCI: Leftover static devices:
PCI: 00:02.2
PCI: 00:02.3
PCI: 00:19.0
PCI: 00:1d.0
PCI: 00:1f.5
PCI: Check your devicetree.cb.
PCI: 00:02.2 - Keep - "off" setting disables the root port
PCI: 00:02.3 - Remove - there is no 2.3 root port
PCI: 00:19.0 - Remove - Gigabit controller is disabled on Mono Lake
PCI: 00:1d.0 - Keep - EHCI enable patch to follow
PCI: 00:1f.5 - Remove - Second SATA device not enabled
Change-Id: I200acdda07f6bd6a060de3c4b4d335d9227216ed
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/ocp/monolake/devicetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 26c95d5d6792..0e3857b1de98 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -5,9 +5,7 @@ chip soc/intel/fsp_broadwell_de device domain 0 on device pci 00.0 on end # SoC router device pci 02.2 off end # IOU0 port C, 10GbE - device pci 02.3 off end # IOU0 port D, 10GbE device pci 14.0 on end # xHCI Controller - device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller device pci 1f.0 on chip drivers/pc80/tpm @@ -20,6 +18,5 @@ chip soc/intel/fsp_broadwell_de end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller - device pci 1f.5 on end # SATA Controller end end |