soc/intel: Add get_pmbase

Originally a part of security/intel/stm.

Add get_pmbase to the intel platform setup code.

get_pmbase is used by the coreboot STM setup functions to ensure
that the pmbase is accessable by the SMI handler during runtime.
The pmbase has to be accounted for in the BIOS resource list so
that the SMI handler is allowed this access.

Original-Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2
Original-Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I7f9ef32946a17aa0bbcbc375bc34b48e62620694
Signed-off-by: Eugene Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

15 files changed, 91 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index d0b04215617a..22e414c803e4 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -250,4 +250,7 @@ void pch_log_state(void);
 
 void enable_pm_timer_emulation(void);
 
+/* STM Support */
+uint16_t get_pmbase(void);
+
 #endif
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 559adad405a3..8151afc08d11 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -246,3 +246,9 @@ int vbnv_cmos_failed(void)
 
 	return rtc_failure;
 }
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+	return (uint16_t) ACPI_BASE_ADDRESS;
+}
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h
index 18004fa77dae..c9074d8a0b9a 100644
--- a/src/soc/intel/broadwell/include/soc/pm.h
+++ b/src/soc/intel/broadwell/include/soc/pm.h
@@ -155,4 +155,7 @@ void disable_gpe(uint32_t mask);
 /* Return the selected ACPI SCI IRQ */
 int acpi_sci_irq(void);
 
+/* STM Support */
+uint16_t get_pmbase(void);
+
 #endif
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 00db6156ec56..2445dfacf6bc 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -458,3 +458,9 @@ int vboot_platform_is_resuming(void)
 
 	return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
 }
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+	return (uint16_t) ACPI_BASE_ADDRESS;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index 5b85e74bf5ec..356f0bcc6fcc 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -172,5 +172,8 @@ void pmc_set_disb(void);
 /* Clear PMCON status bits */
 void pmc_clear_pmcon_sts(void);
 
+/* STM Support */
+uint16_t get_pmbase(void);
+
 #endif /* !defined(__ACPI__) */
 #endif
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 428a89fe4b3d..577487318030 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -273,3 +273,9 @@ void soc_fill_power_state(struct chipset_power_state *ps)
 	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 		ps->gblrst_cause[0], ps->gblrst_cause[1]);
 }
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+	return (uint16_t) ACPI_BASE_ADDRESS;
+}
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pm.h b/src/soc/intel/fsp_broadwell_de/include/soc/pm.h
new file mode 100644
index 000000000000..c1b6ee9e80de
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/pm.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2016-2018 Siemens AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_FSP_BROADWELL_DE_PM_H_
+#define _SOC_FSP_BROADWELL_DE_PM_H_
+
+/*
+ * Brings in get_pmbase so that StmPlatformResource.c can build
+ * under 4.11
+ */
+
+#include <soc/acpi.h>
+#endif
diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h
index 44888ec74723..34c32a9ac202 100644
--- a/src/soc/intel/icelake/include/soc/pm.h
+++ b/src/soc/intel/icelake/include/soc/pm.h
@@ -171,5 +171,8 @@ void pmc_set_disb(void);
 /* Clear PMCON status bits */
 void pmc_clear_pmcon_sts(void);
 
+/* STM Support */
+uint16_t get_pmbase(void);
+
 #endif /* !defined(__ACPI__) */
 #endif
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 8efd426606f6..a4971da98479 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -272,3 +272,9 @@ void soc_fill_power_state(struct chipset_power_state *ps)
 	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 		ps->gblrst_cause[0], ps->gblrst_cause[1]);
 }
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+	return (uint16_t) ACPI_BASE_ADDRESS;
+}
diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c
index ffcd91f13d7c..5006b19d4792 100644
--- a/src/soc/intel/quark/acpi.c
+++ b/src/soc/intel/quark/acpi.c
@@ -104,3 +104,10 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
 	printk(BIOS_SPEW, "  0x%08x: RESET\n", fadt->reset_reg.addrl);
 
 }
+
+uint16_t get_pmbase(void)
+{
+	struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
+		PCI_FUNCTION_NUMBER_QNC_LPC);
+	return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;
+}
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
index a3fb02f7dbd0..e02b8a274e62 100644
--- a/src/soc/intel/quark/include/soc/pm.h
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -27,4 +27,7 @@ struct chipset_power_state {
 struct chipset_power_state *get_power_state(void);
 int fill_power_state(void);
 
+/* STM Support */
+uint16_t get_pmbase(void);
+
 #endif /* _SOC_PM_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 18b0c15d6494..007d29cadce8 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -197,4 +197,7 @@ static inline int deep_s5_enabled(void)
 	return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS));
 }
 
+/* STM Support */
+uint16_t get_pmbase(void);
+
 #endif
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 329cea962136..aac5d1d9393f 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -266,3 +266,9 @@ void soc_fill_power_state(struct chipset_power_state *ps)
 	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 	       ps->gblrst_cause[0], ps->gblrst_cause[1]);
 }
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+	return ACPI_BASE_ADDRESS;
+}
diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h
index fb9b67bc239d..d2f47e271bb5 100644
--- a/src/soc/intel/tigerlake/include/soc/pm.h
+++ b/src/soc/intel/tigerlake/include/soc/pm.h
@@ -177,5 +177,7 @@ void pmc_set_disb(void);
 /* Clear PMCON status bits */
 void pmc_clear_pmcon_sts(void);
 
+/* STM Support */
+uint16_t get_pmbase(void);
 #endif /* !defined(__ACPI__) */
 #endif
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index 53f86097eeb9..39659c3c6fdb 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -274,3 +274,9 @@ void soc_fill_power_state(struct chipset_power_state *ps)
 	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 		ps->gblrst_cause[0], ps->gblrst_cause[1]);
 }
+
+/* STM Support */
+uint16_t get_pmbase(void)
+{
+	return (uint16_t) ACPI_BASE_ADDRESS;
+}