diff options
author | Jonathan Zhang <jonzhang@fb.com> | 2020-05-15 13:37:22 -0700 |
---|---|---|
committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-05-25 10:21:52 +0000 |
commit | 674a825cd7477fc4339ba9b39a676e1a57dfa93c (patch) | |
tree | bb2f077a049b4661056faf74c3c93556ffac1678 | |
parent | 631eac99ed76def62f2687184db10f3348c1da47 (diff) | |
download | coreboot-674a825cd7477fc4339ba9b39a676e1a57dfa93c.tar.gz coreboot-674a825cd7477fc4339ba9b39a676e1a57dfa93c.tar.bz2 coreboot-674a825cd7477fc4339ba9b39a676e1a57dfa93c.zip |
mb/fb/watson/watson_v2: configure PCI bifurcation
Watson V2 server has different PCIe bifurcation configuration, comparing to
Watson server.
Add a watson_v2 variant directory. Allow variant to customize UPD parameters.
Configure UPD parameters to define PCIe bifurcation configuration for Watson
V2 server.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3b57c64dea6f3a468336fcdb1e948dfcd897e60c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-rw-r--r-- | src/mainboard/facebook/watson/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/facebook/watson/Makefile.inc | 2 | ||||
-rw-r--r-- | src/mainboard/facebook/watson/include/variants.h | 25 | ||||
-rw-r--r-- | src/mainboard/facebook/watson/romstage.c | 9 | ||||
-rw-r--r-- | src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc | 1 | ||||
-rw-r--r-- | src/mainboard/facebook/watson/variants/watson_v2/romstage.c | 48 |
6 files changed, 89 insertions, 0 deletions
diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig index 009e8b548635..f8f93df9b1c3 100644 --- a/src/mainboard/facebook/watson/Kconfig +++ b/src/mainboard/facebook/watson/Kconfig @@ -41,6 +41,10 @@ config CBFS_SIZE hex default 0x00800000 +config VARIANT_DIR + string + default "watson_v2" if BOARD_FACEBOOK_WATSON_V2 + config VBOOT_FWID_MODEL string default "$(CONFIG_MAINBOARD_VENDOR)_$(CONFIG_MAINBOARD_PART_NUMBER)" diff --git a/src/mainboard/facebook/watson/Makefile.inc b/src/mainboard/facebook/watson/Makefile.inc index 1606476d805a..f1384f7c97cd 100644 --- a/src/mainboard/facebook/watson/Makefile.inc +++ b/src/mainboard/facebook/watson/Makefile.inc @@ -14,3 +14,5 @@ ## ramstage-y += irqroute.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/facebook/watson/include/variants.h b/src/mainboard/facebook/watson/include/variants.h new file mode 100644 index 000000000000..46989168c98a --- /dev/null +++ b/src/mainboard/facebook/watson/include/variants.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) Facebook, Inc. and its affiliates + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/romstage.h> + +void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/facebook/watson/romstage.c b/src/mainboard/facebook/watson/romstage.c index cf52c01f0466..b8df79803192 100644 --- a/src/mainboard/facebook/watson/romstage.c +++ b/src/mainboard/facebook/watson/romstage.c @@ -17,6 +17,7 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <variants.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -41,5 +42,13 @@ void late_mainboard_romstage_entry(void) */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + + /* Variant-specific memory params */ + variant_romstage_fsp_init_params(UpdData); +} + +__weak void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData) +{ } diff --git a/src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc b/src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc new file mode 100644 index 000000000000..29763fb4f6bb --- /dev/null +++ b/src/mainboard/facebook/watson/variants/watson_v2/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/mainboard/facebook/watson/variants/watson_v2/romstage.c b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c new file mode 100644 index 000000000000..55f30255e8ec --- /dev/null +++ b/src/mainboard/facebook/watson/variants/watson_v2/romstage.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) Facebook, Inc. and its affiliates + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <variants.h> + +void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData) +{ + /* Configure IOU1 as 4*4 lanes */ + UpdData->ConfigIOU1_PciPort3 = 0; + + /* Configure IOU2 as 2*4 lanes */ + UpdData->ConfigIOU2_PciPort1 = 0; + + /* Configure PCH PCIe ports as 8*1 lanes */ + UpdData->PchPciPort1 = 1; + UpdData->PchPciPort2 = 1; + UpdData->PchPciPort3 = 1; + UpdData->PchPciPort4 = 1; + UpdData->PchPciPort5 = 1; + UpdData->PchPciPort6 = 1; + UpdData->PchPciPort7 = 1; + UpdData->PchPciPort8 = 1; + + /* Enable hotplug for PCH PCIe ports */ + UpdData->HotPlug_PchPciPort1 = 1; + UpdData->HotPlug_PchPciPort2 = 1; + UpdData->HotPlug_PchPciPort3 = 1; + UpdData->HotPlug_PchPciPort4 = 1; + UpdData->HotPlug_PchPciPort5 = 1; + UpdData->HotPlug_PchPciPort6 = 1; + UpdData->HotPlug_PchPciPort7 = 1; + UpdData->HotPlug_PchPciPort8 = 1; +} |