diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2021-03-22 16:12:05 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-24 07:53:52 +0000 |
| commit | 8b22c558554c3722cbd809fac132a5ca46451280 (patch) | |
| tree | f3833912ae93b8ac85f0b7499532154c739c7fe9 | |
| parent | 570ae23516593e243e29750f4b61a1b841a5ad27 (diff) | |
| download | coreboot-8b22c558554c3722cbd809fac132a5ca46451280.tar.gz coreboot-8b22c558554c3722cbd809fac132a5ca46451280.tar.bz2 coreboot-8b22c558554c3722cbd809fac132a5ca46451280.zip | |
soc/intel/fsp_broadwell_de: Add definition for LGMR
Add definition for LPC Generic Memory Range register.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7c76bacdf692e72849547106f29b614345f505c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51716
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/include/soc/lpc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h index 3f9c2024f724..01e5a5b28d41 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h @@ -37,6 +37,7 @@ #define LPC_GEN2_DEC 0x88 #define LPC_GEN3_DEC 0x8c #define LPC_GEN4_DEC 0x90 +#define LGMR 0x98 /* LPC Generic Memory Range */ #define GEN_PMCON_1 0xA0 #define SMI_LOCK (1 << 4) #define SMI_LOCK_GP6 (1 << 5) |