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| author | Jonathan Zhang <jonzhang@fb.com> | 2021-03-22 16:23:38 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-28 16:07:17 +0000 |
| commit | 9f53477768156bfe29403f6facc10552e53a2d64 (patch) | |
| tree | e6fe012bc067f604f52ab0e486e46dce7e27572e | |
| parent | 8b22c558554c3722cbd809fac132a5ca46451280 (diff) | |
| download | coreboot-9f53477768156bfe29403f6facc10552e53a2d64.tar.gz coreboot-9f53477768156bfe29403f6facc10552e53a2d64.tar.bz2 coreboot-9f53477768156bfe29403f6facc10552e53a2d64.zip | |
soc/intel/fsp_broadwell_de: Set up LPC Generic Memory Range register
If mainboard devicetree config defines lpc_lgmr, use it to
set up LPC Generic Memory Range register. Also set up
64KiB memory resource.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iec94f7364c332789f75c2562e910ea5db4ffad23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51717
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/southcluster.c | 12 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/chip.h b/src/soc/intel/fsp_broadwell_de/chip.h index bf2896238a54..95c1c2d9594b 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.h +++ b/src/soc/intel/fsp_broadwell_de/chip.h @@ -25,6 +25,8 @@ struct soc_intel_fsp_broadwell_de_config { /* PCIe completion timeout value */ int pcie_compltoval; + /* LPC Generic Memory Range Register value */ + uint32_t lpc_lgmr; }; typedef struct soc_intel_fsp_broadwell_de_config config_t; diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index fb8af87b625e..df562f133dd5 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -28,6 +28,7 @@ #include <pc80/i8259.h> #include <pc80/isa-dma.h> #include <soc/iomap.h> +#include <soc/intel/common/block/lpc/lpc_def.h> #include <soc/irq.h> #include <soc/lpc.h> #include <soc/pci_devs.h> @@ -216,6 +217,17 @@ static void sc_read_resources(struct device *dev) pci_dev_read_resources(dev); sc_add_mmio_resources(dev); sc_add_io_resources(dev); + + const config_t *config = config_of_soc(); + if (config->lpc_lgmr) { + struct resource *res; + res = new_resource(dev, LGMR); + res->base = config->lpc_lgmr & ~(LPC_LGMR_EN); + res->size = 64 * KiB; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED + | IORESOURCE_RESERVE; + pci_write_config32(dev, LGMR, config->lpc_lgmr); + } } static void sc_init(struct device *dev) |