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| author | Nico Huber <nico.h@gmx.de> | 2020-07-06 21:14:02 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 12:25:41 +0000 |
| commit | b43431d58e047783783e190ba684de28b9222443 (patch) | |
| tree | 6f006e66c4721667ec2904f975a66db883a6c44e | |
| parent | fabe8f5a9552c789f7b0cee3caaa72b20c06f6ac (diff) | |
| download | coreboot-b43431d58e047783783e190ba684de28b9222443.tar.gz coreboot-b43431d58e047783783e190ba684de28b9222443.tar.bz2 coreboot-b43431d58e047783783e190ba684de28b9222443.zip | |
mb/lenovo/t60: Fix override devicetrees
Commit c1dc2d5e68 (mb/lenovo/t60: Switch to override tree) converted
these boards to override trees, but some device nodes were missed.
Said nodes are essential, as `chip` configuration data is always tied
to device nodes. The resulting `static.c` contained multiple copies
of the `chip` configuration structs, but the wrong ones were hooked up.
The therefore missing configuration of the clockgen led to general
instability, especially with SMP under Linux (probably due to the
attempt to enter lower C states on an idle core). Passing `maxcpus=1`
to the Linux kernel served as a workaround.
Change-Id: I6c26d633d1860cf9a5415994444e75ae1c2e59ad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43065
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/lenovo/t60/variants/t60/overridetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t60/variants/z61t/overridetree.cb | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb index eee3a4d57525..551fff3771ba 100644 --- a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -44,6 +44,7 @@ chip northbridge/intel/i945 register "has_bdc_detection" = "1" register "bdc_gpio_num" = "7" register "bdc_gpio_lvl" = "0" + device pnp ff.2 on end end chip superio/nsc/pc87384 device pnp 2e.2 off # Serial Port / IR @@ -62,6 +63,7 @@ chip northbridge/intel/i945 register "regs" = "{ 0x2e, 0xf7, 0x3c, 0x20, 0x01, 0x00, 0x1b, 0x01, 0x54, 0xff, 0xff, 0x07 }" + device i2c 69 on end end end end diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb index d29df3b48824..c372b18e3838 100644 --- a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -57,6 +57,7 @@ chip northbridge/intel/i945 # vendor clockgen setup register "regs" = "{ 0x6d, 0xff, 0xff, 0x20, 0x41, 0x7f, 0x18, 0x00 }" + device i2c 69 on end end end end |