diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-05-02 16:52:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-05 22:41:29 +0200 |
| commit | f49785e8e2ab0fa274d538ba2ecf36881fe4529a (patch) | |
| tree | 7ae11526d80d73489af593afb00256550256664a | |
| parent | e311f94279de87f31b94d47cc46c43f0dd7741ef (diff) | |
| download | coreboot-f49785e8e2ab0fa274d538ba2ecf36881fe4529a.tar.gz coreboot-f49785e8e2ab0fa274d538ba2ecf36881fe4529a.tar.bz2 coreboot-f49785e8e2ab0fa274d538ba2ecf36881fe4529a.zip | |
google/fizz: Enable devices under pci 1c.0
Turn on device 1c.0 in order to enable devices
under it.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=Boot from NVMe
Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19533
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index e18b76701e00..ff2ec7f86d56 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -228,7 +228,7 @@ chip soc/intel/skylake device pci 19.1 on end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 on end # PCI Express Port 3 for LAN device pci 1c.3 on |