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| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-02 16:46:44 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2020-05-12 06:45:38 +0000 |
| commit | 2b6bb79fe46b020ad4568da90c8c4d819ea2885b (patch) | |
| tree | e00e38f7e2bc91a06bd89acc2ae392f3e3c2ad92 | |
| parent | 561b8cc2e7469af7ad0796304a0c51684551e59a (diff) | |
| download | coreboot-2b6bb79fe46b020ad4568da90c8c4d819ea2885b.tar.gz coreboot-2b6bb79fe46b020ad4568da90c8c4d819ea2885b.tar.bz2 coreboot-2b6bb79fe46b020ad4568da90c8c4d819ea2885b.zip | |
nb/intel/sandybridge: Reorder register write
Reorder the order of the operands in three register writes, so that
replacing them with macros in a follow-up does not change the binary.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40972
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 19b72cb18ec0..34d82fce5f61 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -667,21 +667,21 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command MRS */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command MRS */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* Execute command queue */ |