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| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-02 16:51:39 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2020-05-12 06:45:59 +0000 |
| commit | c36cd07f9eb6cf3858b0ddc187e22cfd32b600c7 (patch) | |
| tree | 10add2e0987826f6fd30f4c43eb07a2f5b1b139a | |
| parent | 2b6bb79fe46b020ad4568da90c8c4d819ea2885b (diff) | |
| download | coreboot-c36cd07f9eb6cf3858b0ddc187e22cfd32b600c7.tar.gz coreboot-c36cd07f9eb6cf3858b0ddc187e22cfd32b600c7.tar.bz2 coreboot-c36cd07f9eb6cf3858b0ddc187e22cfd32b600c7.zip | |
nb/intel/sandybridge: Reorder IOSAV writes
We only write to the IOSAV LFSR registers twice, but we do so between
the writes to the other four IOSAV per-subsequence registers. Since we
know that the IOSAV is sleeping when we program the subsequences, we
might as well do the two oddball LFSR register writes after we have
programmed the always-written-to group of four registers. That way,
subsequent changes can reproducibly replace the four writes with a
single macro.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: If7bb14a9862a53a3eba565d17401347dcc9ffbe9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40973
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 34d82fce5f61..05cffd3fd8c4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2030,16 +2030,16 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x20e42; + MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; /* DRAM command RD */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x20e42; + MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; /* DRAM command PRE */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; |