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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-11 11:17:30 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-20 00:47:05 +0000 |
| commit | 051ee4e3ad14861b64ddb1da5af473812770279a (patch) | |
| tree | 6df20db85d8ae352babd61a5f9d0ac8802c740f9 | |
| parent | 0f91e9ce5f53db70bf738f66988603156021d7c7 (diff) | |
| download | coreboot-051ee4e3ad14861b64ddb1da5af473812770279a.tar.gz coreboot-051ee4e3ad14861b64ddb1da5af473812770279a.tar.bz2 coreboot-051ee4e3ad14861b64ddb1da5af473812770279a.zip | |
soc/intel/xeon_sp: Lock down DMICTL
This is required for CBnT.
Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47449
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/xeon_sp/pch.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 5427952688e2..2b35223d162a 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -39,6 +39,9 @@ static void soc_config_acpibase(void) reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); + + reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } void bootblock_pch_init(void) |