soc/mediatek/mt8192: Enable MT8192 auxadc driver

Enable reading from auxadc on MediaTek 8192 platform.

Reference datasheet: RH-A-2020-0070, v1.0

Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: Ic4c965fc3571637d882eb297e405a5d9e6f77dd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

4 files changed, 46 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 3237d409c094..07a13af5f33c 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -1,5 +1,6 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y)
 
+bootblock-y += ../common/auxadc.c
 bootblock-y += bootblock.c
 bootblock-y += flash_controller.c
 bootblock-y += ../common/gpio.c gpio.c
@@ -13,12 +14,14 @@ bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c
 bootblock-y += mt6315.c
 bootblock-y += mt6359p.c
 
+verstage-y += ../common/auxadc.c
 verstage-y += flash_controller.c
 verstage-y += ../common/gpio.c gpio.c
 verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 verstage-y += ../common/timer.c
 verstage-y += ../common/uart.c
 
+romstage-y += ../common/auxadc.c
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-y += flash_controller.c
@@ -31,6 +34,7 @@ romstage-y += ../common/uart.c
 romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c
 romstage-y += mt6359p.c
 
+ramstage-y += ../common/auxadc.c
 ramstage-y += flash_controller.c
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += emi.c
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index 69d31577028d..12094ffe5d59 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -25,6 +25,7 @@ enum {
 	PMIF_SPMI_BASE		= IO_PHYS + 0x00027000,
 	PMICSPI_MST_BASE	= IO_PHYS + 0x00028000,
 	SPMI_MST_BASE		= IO_PHYS + 0x00029000,
+	AUXADC_BASE		= IO_PHYS + 0x01001000,
 	UART0_BASE		= IO_PHYS + 0x01002000,
 	SPI0_BASE		= IO_PHYS + 0x0100A000,
 	SPI1_BASE		= IO_PHYS + 0x01010000,
@@ -36,6 +37,7 @@ enum {
 	SPI7_BASE		= IO_PHYS + 0x0101E000,
 	SSUSB_IPPC_BASE		= IO_PHYS + 0x01203e00,
 	SFLASH_REG_BASE		= IO_PHYS + 0x01234000,
+	EFUSEC_BASE		= IO_PHYS + 0x01C10000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01C20000,
 	IOCFG_BM_BASE		= IO_PHYS + 0x01D10000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01D30000,
diff --git a/src/soc/mediatek/mt8192/include/soc/auxadc.h b/src/soc/mediatek/mt8192/include/soc/auxadc.h
new file mode 100644
index 000000000000..3289a22ccf42
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/auxadc.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MTK_ADC_H
+#define _MTK_ADC_H
+
+#include <soc/auxadc_common.h>
+#include <soc/infracfg.h>
+#include <stdint.h>
+
+typedef struct mtk_auxadc_regs {
+	uint32_t con0;
+	uint32_t con1;
+	uint32_t con1_set;
+	uint32_t con1_clr;
+	uint32_t con2;
+	uint32_t data[16];
+	uint32_t reserved[16];
+	uint32_t misc;
+} mtk_auxadc_regs;
+
+static struct mt8192_infracfg_regs *const mtk_infracfg = mt8192_infracfg;
+
+#endif
diff --git a/src/soc/mediatek/mt8192/include/soc/efuse.h b/src/soc/mediatek/mt8192/include/soc/efuse.h
new file mode 100644
index 000000000000..f0f3405a5a90
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/efuse.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MTK_EFUSE_H
+#define _MTK_EFUSE_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct efuse_regs {
+	uint32_t rserved[109];
+	uint32_t adc_cali_reg;
+};
+
+check_member(efuse_regs, adc_cali_reg, 0x1b4);
+static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE;
+
+#endif