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| author | Raul E Rangel <rrangel@chromium.org> | 2021-05-07 12:30:49 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-09 18:11:37 +0000 |
| commit | 506ee24e24d6c30f75063fc869246aeec072ea7b (patch) | |
| tree | 7597c33ed54173b2f0a21db099845a9a3926bb9f | |
| parent | 1ed5a63c8c8b2680ee4371427aa6482a59777326 (diff) | |
| download | coreboot-506ee24e24d6c30f75063fc869246aeec072ea7b.tar.gz coreboot-506ee24e24d6c30f75063fc869246aeec072ea7b.tar.bz2 coreboot-506ee24e24d6c30f75063fc869246aeec072ea7b.zip | |
soc/amd/cezanne: Enable GNB IO-APIC _PRT
We can now use the GNB IO-APIC.
BUG=b:184766519
TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic`
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4df5a4583f14044d2efcde3a9de9dd85e898a11d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53936
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/cezanne/pcie_gpp.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/cezanne/pcie_gpp.c index 16c6b2324395..283470bc2758 100644 --- a/src/soc/amd/cezanne/pcie_gpp.c +++ b/src/soc/amd/cezanne/pcie_gpp.c @@ -65,8 +65,7 @@ static void acpi_device_write_gpp_pci_dev(const struct device *dev) acpigen_write_ADR_pci_device(dev); acpigen_write_STA(acpi_device_status(dev)); - /* b/187083211 - Enable GNB IO-APIC */ - acpigen_write_pci_FCH_PRT(dev); + acpigen_write_pci_GNB_PRT(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ |