diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2021-05-04 09:49:18 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-07 06:05:18 +0000 |
| commit | 7b7b33e3a615b0581df9e8e371fb218e97ba2a51 (patch) | |
| tree | fa8a3d9d035a721d2092fdf49a1316ba612d9bc6 | |
| parent | 4f27dde72aaaa203113fb29acca6fc3b88b89de4 (diff) | |
| download | coreboot-7b7b33e3a615b0581df9e8e371fb218e97ba2a51.tar.gz coreboot-7b7b33e3a615b0581df9e8e371fb218e97ba2a51.tar.bz2 coreboot-7b7b33e3a615b0581df9e8e371fb218e97ba2a51.zip | |
soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
If a power button SMI is triggered between where it is currently
enabled and before FSP-S exits, when the SMI handler disables
bus mastering for all devices, it inadvertently also disables
the PMC's I/O decoding, so the register write to actually go into
S5 does not succeed, and the system hangs.
This can be solved by skipping the PMC when disabling bus
mastering in the SMI handler, for which a callback,
smihandler_soc_disable_busmaster is provided.
BUG=b:186194102, b:186815114
TEST=Power on the system and pressing power button repeatedly doesn't
cause the system hang during shutdown.
Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/soc/intel/alderlake/smihandler.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/smihandler.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/smihandler.c | 8 |
3 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index a072138c96db..5b5303883499 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -24,6 +24,14 @@ void smihandler_soc_at_finalize(void) heci_disable(); } +int smihandler_soc_disable_busmaster(pci_devfn_t dev) +{ + /* Skip disabling PMC bus master to keep IO decode enabled */ + if (dev == PCH_DEV_PMC) + return 0; + return 1; +} + const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 448c0539d728..2e38b68768b2 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -24,6 +24,14 @@ void smihandler_soc_at_finalize(void) heci_disable(); } +int smihandler_soc_disable_busmaster(pci_devfn_t dev) +{ + /* Skip disabling PMC bus master to keep IO decode enabled */ + if (dev == PCH_DEV_PMC) + return 0; + return 1; +} + const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 67d21f8e33e9..6280fb28bddc 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -24,6 +24,14 @@ void smihandler_soc_at_finalize(void) heci_disable(); } +int smihandler_soc_disable_busmaster(pci_devfn_t dev) +{ + /* Skip disabling PMC bus master to keep IO decode enabled */ + if (dev == PCH_DEV_PMC) + return 0; + return 1; +} + const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, |