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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2021-04-29 17:53:10 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-07 12:46:17 +0000 |
| commit | 8e23270405b4ecd27abb02af9cc8a985aa01edcf (patch) | |
| tree | ca4a76c90fe1eb09c00188d90c842e7c2da08bb6 | |
| parent | 27be90424b7cb8fd51c7ff6b6812601b9d091b6b (diff) | |
| download | coreboot-8e23270405b4ecd27abb02af9cc8a985aa01edcf.tar.gz coreboot-8e23270405b4ecd27abb02af9cc8a985aa01edcf.tar.bz2 coreboot-8e23270405b4ecd27abb02af9cc8a985aa01edcf.zip | |
mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.
TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/mainboard/pcengines/apu2/OemCustomize.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6e6b5a273a74..95af6ef92d56 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -3,6 +3,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/state_machine.h> +#include "gpio_ftns.h" + static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -78,3 +80,17 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CpbMode = CpbModeAuto; } + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* + * Bank interleaving does not work on this platform. + * Disable it so AGESA will return success. + */ + Post->MemConfig.EnableBankIntlv = FALSE; + /* 4GB variants have ECC */ + if (get_spd_offset()) + Post->MemConfig.EnableEccFeature = TRUE; + else + Post->MemConfig.EnableEccFeature = FALSE; +} |