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| author | Felix Singer <felixsinger@posteo.net> | 2021-04-19 01:59:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-10 14:17:48 +0000 |
| commit | 929b65add452952973b59e005fda1ee064900850 (patch) | |
| tree | 1d4855e00334cbd5f5fbef58cc0d4a09f2fc763e | |
| parent | 1f44efc2028575fcf940ef188f62bf3730a3d81d (diff) | |
| download | coreboot-929b65add452952973b59e005fda1ee064900850.tar.gz coreboot-929b65add452952973b59e005fda1ee064900850.tar.bz2 coreboot-929b65add452952973b59e005fda1ee064900850.zip | |
soc/intel/cannonlake: Merge soc_memory_init_params() into its caller
soc_memory_init_params() does not only configure memory init parameters.
Despite its name, it also configures many other things. Therefore, merge
it into its caller function platform_fsp_memory_init_params_cb() to
prevent confusions.
Built clevo/l140cu with BUILD_TIMELESS=1. coreboot.rom remains the same.
Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52491
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5eddf85770c1..2bb3024e090a 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -17,19 +17,21 @@ #include "../chip.h" -static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + assert(dev != NULL); + const config_t *config = config_of(dev); FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - unsigned int i; uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); /* * Probe for no IGD and disable InternalGfx and panel power to prevent a * crash in FSP-M. */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { /* Set IGD stolen size to 64MB. */ @@ -131,17 +133,6 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) if (config->DisableHeciRetry) tconfig->DisableHeciRetry = config->DisableHeciRetry; #endif -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - assert(dev != NULL); - const config_t *config = config_of(dev); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - - soc_memory_init_params(mupd, config); /* Enable SMBus controller based on config */ dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); |