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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-03-16 16:27:27 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-05 12:03:26 +0000 |
| commit | be2f937f1ef51cb791739eae1fc00c441bb06860 (patch) | |
| tree | 7f62fd62cb821f515aec85c120014d2034a2cbd4 | |
| parent | c8116f6ea062dc60c6efd6a73510e69eb9b84c2d (diff) | |
| download | coreboot-be2f937f1ef51cb791739eae1fc00c441bb06860.tar.gz coreboot-be2f937f1ef51cb791739eae1fc00c441bb06860.tar.bz2 coreboot-be2f937f1ef51cb791739eae1fc00c441bb06860.zip | |
soc/intel/xeon_sp: Remove bogus SMRAM locking
From tests this does not lock down SMRAM and it's also not possible to
read back what is written, be it via PCI mmconfig or io ops. The
FSP integration can be assumed to be bogus on this point.
Change-Id: Ia0526774f7b201d2a3c0eefb578bf0a19dae9212
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51532
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 3eaf46f1cf63..9164b7cbe79c 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -182,14 +182,6 @@ static void chip_final(void *data) /* LOCK PAM */ pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); - /* - * LOCK SMRAM - * According to the CedarIsland FSP Integration Guide this needs to - * be done with legacy 0xCF8/0xCFC IO ops. - */ - uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); - pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); - mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); set_imc_locks(); |