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| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-11-04 13:56:56 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-05 12:59:42 +0000 |
| commit | 0d50892e841d751bfcb20fdd56adde4f1b244a26 (patch) | |
| tree | 48a8bb6eaf49552d32765525322e65584420d6f5 | |
| parent | 3aa61136cc2225087626191a1b67d8bf2470e1dd (diff) | |
| download | coreboot-0d50892e841d751bfcb20fdd56adde4f1b244a26.tar.gz coreboot-0d50892e841d751bfcb20fdd56adde4f1b244a26.tar.bz2 coreboot-0d50892e841d751bfcb20fdd56adde4f1b244a26.zip | |
soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder
The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so we have to
provide an init function in SoC for the mainboard to select right
configuration.
TEST=boot to romstage
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/spi.h | 8 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/spi.c | 39 |
2 files changed, 47 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h index cf6466083774..fbf3995b7af0 100644 --- a/src/soc/mediatek/mt8186/include/soc/spi.h +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -10,4 +10,12 @@ #include <spi-generic.h> +enum { + SPI_NOR_GPIO_SET0 = 0, + SPI_NOR_GPIO_SET1, + SPI_NOR_GPIO_SET_NUM, +}; + +void mtk_snfc_init(int gpio_set); + #endif diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index e72b50f3d510..4a1c13caa562 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -5,11 +5,50 @@ * Chapter number: 5.6, 5.8 */ +#include <assert.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/flash_controller_common.h> +#include <soc/gpio.h> #include <soc/spi.h> +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4] = { + /* GPIO 36 ~ 39 */ + [SPI_NOR_GPIO_SET0] = { + PAD_FUNC(SPI0_CLK, SPINOR_CK), + PAD_FUNC(SPI0_CSB, SPINOR_CS), + PAD_FUNC(SPI0_MO, SPINOR_IO0), + PAD_FUNC(SPI0_MI, SPINOR_IO1), + }, + /* GPIO 61 ~ 64 */ + [SPI_NOR_GPIO_SET1] = { + PAD_FUNC(TDM_RX_BCK, SPINOR_CK), + PAD_FUNC(TDM_RX_MCLK, SPINOR_CS), + PAD_FUNC(TDM_RX_DATA0, SPINOR_IO0), + PAD_FUNC(TDM_RX_DATA1, SPINOR_IO1), + }, +}; + +void mtk_snfc_init(int gpio_set) +{ + const struct pad_func *ptr = NULL; + + assert(gpio_set < SPI_NOR_GPIO_SET_NUM); + + ptr = nor_pinmux[gpio_set]; + for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) { + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode(ptr[i].gpio, ptr[i].func); + } +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, |