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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2021-11-02 10:55:56 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-04 10:22:07 +0000 |
| commit | 17641208f5456b65b6d2660683c01e0506f8c619 (patch) | |
| tree | 028dc74d75aa8b24d2d9c2a3c7c325a552082975 | |
| parent | f9014bbb60b1a4fdfd7aad90579f01dd8e42b1bc (diff) | |
| download | coreboot-17641208f5456b65b6d2660683c01e0506f8c619.tar.gz coreboot-17641208f5456b65b6d2660683c01e0506f8c619.tar.bz2 coreboot-17641208f5456b65b6d2660683c01e0506f8c619.zip | |
mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
On mc_ehl2 there are currently four of the six PCIe clocks used to drive
PCIe devices. None of the used clock output is dedicated to a special
device. Therefore do not use a port mapping of the clocks to avoid a
stopping clock once a device is missing and the matching root port is
disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free
running clock.
In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.
Change-Id: I81419887b7f463a937917b971465245c1cb46b94
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 451c5dd5f233..8b9e9e24501f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -55,19 +55,19 @@ chip soc/intel/elkhartlake register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" - register "PcieClkSrcUsage[1]" = "0x01" - register "PcieClkSrcUsage[2]" = "0x02" - register "PcieClkSrcUsage[3]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" - - register "PcieClkSrcClkReq[0]" = "0xFF" - register "PcieClkSrcClkReq[1]" = "0xFF" - register "PcieClkSrcClkReq[2]" = "0xFF" - register "PcieClkSrcClkReq[3]" = "0xFF" - register "PcieClkSrcClkReq[4]" = "0xFF" - register "PcieClkSrcClkReq[5]" = "0xFF" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" |