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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-04-22 16:59:08 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:28:29 +0000 |
| commit | 5ad85d95cd656996acbfef5c8bea791662b551cd (patch) | |
| tree | db3452af1dc4f584c7b1257fe8229dcd13917020 | |
| parent | 250e610fa082473b3592d06c69316ec1daa88116 (diff) | |
| download | coreboot-5ad85d95cd656996acbfef5c8bea791662b551cd.tar.gz coreboot-5ad85d95cd656996acbfef5c8bea791662b551cd.tar.bz2 coreboot-5ad85d95cd656996acbfef5c8bea791662b551cd.zip | |
soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPD
Configure the S0i3 enable UPD based on the mainboard configuration.
BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 9d4159d85b65..a83b8b2f5768 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -113,5 +113,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->cppc_epp_min_range = config->cppc_epp_min_range; mcfg->cppc_preferred_cores = config->cppc_preferred_cores; + /* S0i3 enable */ + mcfg->s0i3_enable = config->s0ix_enable; + fsp_fill_pcie_ddi_descriptors(mcfg); } |