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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2021-11-02 13:03:29 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-04 10:22:30 +0000 |
| commit | 5c65ec1ee51b93e41c1e123c24643ea2faec29d1 (patch) | |
| tree | 72efe362ba7be6d701287902343d9e83830447c2 | |
| parent | 8aac54d43abef86232471b3e0a214f08675013ff (diff) | |
| download | coreboot-5c65ec1ee51b93e41c1e123c24643ea2faec29d1.tar.gz coreboot-5c65ec1ee51b93e41c1e123c24643ea2faec29d1.tar.bz2 coreboot-5c65ec1ee51b93e41c1e123c24643ea2faec29d1.zip | |
mb/siemens/mc_ehl2: Configure SD card detect pin in devicetree
This configures GPIO GPP_G5 as an input pin for SD card detect.
Change-Id: I708eb112fa054f2f88857001c409fb62493b6206
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 701efb41c0b0..0ff38d79925e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -92,6 +92,9 @@ chip soc/intel/elkhartlake register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, |