soc/intel/jasperlake: Set xHCI LFPS period sampling off time

Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.

The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.

BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

4 files changed, 53 insertions, 1 deletions

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 9064297c74d8..cb5321c77380 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -206,6 +206,9 @@ chip soc/intel/jasperlake
 	# Enable HECI
 	register "HeciEnabled" = "1"
 
+	# Set xHCI LFPS period sampling off time, the default is 9ms.
+	register "xhci_lfps_sampling_offtime_ms" = "9"
+
 	device domain 0 on
 		device pci 00.0 on end # Host Bridge
 		device pci 02.0 on end # Integrated Graphics Device
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index abb5dc83a1cb..34f9eaeea135 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -174,6 +174,9 @@ chip soc/intel/jasperlake
 	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
 	register "PchPmPwrCycDur" = "1"       # 1s
 
+	# Set xHCI LFPS period sampling off time, the default is 9ms.
+	register "xhci_lfps_sampling_offtime_ms" = "9"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 36e9a1350b2b..4a9d9a0cf17e 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -85,6 +85,11 @@ struct soc_intel_jasperlake_config {
 	/* Wake Enable Bitmap for USB3 ports */
 	uint16_t usb3_wake_enable_bitmap;
 
+	/* Set the LFPS periodic sampling off time for USB3 Ports.
+	   Default value of PMCTRL_REG bits[7:4] is 9 which means periodic
+	   sampling off interval is 9ms, the range is from 0 to 15. */
+	uint8_t xhci_lfps_sampling_offtime_ms;
+
 	/* SATA related */
 	uint8_t SataMode;
 	uint8_t SataSalpSupport;
diff --git a/src/soc/intel/jasperlake/xhci.c b/src/soc/intel/jasperlake/xhci.c
index eebacca9eb3b..75663795d372 100644
--- a/src/soc/intel/jasperlake/xhci.c
+++ b/src/soc/intel/jasperlake/xhci.c
@@ -1,13 +1,20 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/pci_type.h>
+#include <console/console.h>
+#include <device/mmio.h>
 #include <intelblocks/xhci.h>
+#include <soc/soc_chip.h>
 
 #define XHCI_USB2_PORT_STATUS_REG	0x480
 #define XHCI_USB3_PORT_STATUS_REG	0x500
 #define XHCI_USB2_PORT_NUM		8
 #define XHCI_USB3_PORT_NUM		6
 
+#define XHCI_PMCTRL			0x80A4
+/* BIT[7:4] LFPS periodic sampling off time for USB3 Ports */
+#define PMCTRL_LFPS_OFFTIME_SHIFT	4
+#define PMCTRL_LFPS_OFFTIME_MAX		0xF
+
 static const struct xhci_usb_info usb_info = {
 	.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
 	.num_usb2_ports = XHCI_USB2_PORT_NUM,
@@ -20,3 +27,37 @@ const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
 	/* Jasper Lake only has one XHCI controller */
 	return &usb_info;
 }
+
+static void set_xhci_lfps_sampling_offtime(struct device *dev, uint8_t time_ms)
+{
+	void *addr;
+	const struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+
+	if (!res)
+		return;
+
+	if (time_ms > PMCTRL_LFPS_OFFTIME_MAX) {
+		printk(BIOS_ERR,
+			"XHCI: The maximum LFPS sampling OFF time is %u ms, "
+			"cannot set it to %u ms\n",
+			PMCTRL_LFPS_OFFTIME_MAX, time_ms);
+
+		return;
+	}
+
+	addr = (void *)(uintptr_t)(res->base + XHCI_PMCTRL);
+	clrsetbits32(addr,
+		PMCTRL_LFPS_OFFTIME_MAX << PMCTRL_LFPS_OFFTIME_SHIFT,
+		time_ms << PMCTRL_LFPS_OFFTIME_SHIFT);
+	printk(BIOS_DEBUG,
+		"XHCI: Updated LFPS sampling OFF time to %u ms\n", time_ms);
+}
+
+void soc_xhci_init(struct device *dev)
+{
+	const config_t *config = config_of_soc();
+
+	/* Set xHCI LFPS period sampling off time */
+	set_xhci_lfps_sampling_offtime(dev,
+		config->xhci_lfps_sampling_offtime_ms);
+}