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| author | Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> | 2021-11-04 19:35:31 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-05 12:57:42 +0000 |
| commit | 70701eba8db6604b55320fa30b46be5046421fa5 (patch) | |
| tree | 5273f08a6afefdabf4eb9cf81f23d0029d65f9c9 | |
| parent | d74f6f5a5d0a95e4c3b499ae730ef98c7a8260cd (diff) | |
| download | coreboot-70701eba8db6604b55320fa30b46be5046421fa5.tar.gz coreboot-70701eba8db6604b55320fa30b46be5046421fa5.tar.bz2 coreboot-70701eba8db6604b55320fa30b46be5046421fa5.zip | |
mb/google/taeko: Update the FIVR configurations
This patch sets the enable the external voltage rails since taeko
board have V1p05 and Vnn bypass rails.
BRANCH=None
BUG=b:204832954
TEST=FW_NAME=Check in FSP log and run PLT test
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/taeko/overridetree.cb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 4398fa5e7446..8ad5479ac603 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -41,6 +41,19 @@ fw_config end end chip soc/intel/alderlake + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "SaGv" = "SaGv_Enabled" |