diff options
| author | Chun-Jie Chen <chun-jie.chen@mediatek.corp-partner.google.com> | 2021-09-24 18:41:06 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-05 13:03:10 +0000 |
| commit | 76e0b9d710092f1ad73115643b8bb0dd29f46e59 (patch) | |
| tree | 28b898e9e121af872c2880a7ee44ff87c1cf3864 | |
| parent | f1226963a120ee8533e168a12093e08229006db8 (diff) | |
| download | coreboot-76e0b9d710092f1ad73115643b8bb0dd29f46e59.tar.gz coreboot-76e0b9d710092f1ad73115643b8bb0dd29f46e59.tar.bz2 coreboot-76e0b9d710092f1ad73115643b8bb0dd29f46e59.zip | |
soc/mediatek/mt8186: Add PLL and clock init support
Add PLL and clock init code, frequency meter and APIs for
raising little CPU/CCI frequency.
TEST=build pass
BUG=b:202871018
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/soc/mediatek/mt8186/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/infracfg.h | 547 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/mcucfg.h | 947 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/pll.h | 487 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/pll.c | 543 |
6 files changed, 2527 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 366c70676c31..cba4ccfe4020 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -4,6 +4,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c index 770c6031dabf..8dffe5671b89 100644 --- a/src/soc/mediatek/mt8186/bootblock.c +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -2,10 +2,12 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/pll.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); mtk_wdt_init(); + mt_pll_init(); } diff --git a/src/soc/mediatek/mt8186/include/soc/infracfg.h b/src/soc/mediatek/mt8186/include/soc/infracfg.h new file mode 100644 index 000000000000..00400e0bc31d --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/infracfg.h @@ -0,0 +1,547 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.5 + */ + +#ifndef SOC_MEDIATEK_MT8186_INFRACFG_H +#define SOC_MEDIATEK_MT8186_INFRACFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8186_infracfg_ao_regs { + u32 reserved1[20]; + u32 infra_globalcon_dcmctl; + u32 reserved2[7]; + u32 infra_bus_dcm_ctrl; + u32 peri_bus_dcm_ctrl; + u32 mem_dcm_ctrl; + u32 dfs_mem_dcm_ctrl; + u32 module_sw_cg_0_set; + u32 module_sw_cg_0_clr; + u32 module_sw_cg_1_set; + u32 module_sw_cg_1_clr; + u32 module_sw_cg_0_sta; + u32 module_sw_cg_1_sta; + u32 module_clk_sel; + u32 mem_cg_ctrl; + u32 p2p_rx_clk_on; + u32 module_sw_cg_2_set; + u32 module_sw_cg_2_clr; + u32 module_sw_cg_2_sta; + u32 reserved3[1]; + u32 dramc_wbr; + u32 ddr_en_mask; + u32 reserved4[1]; + u32 module_sw_cg_3_set; + u32 module_sw_cg_3_clr; + u32 module_sw_cg_3_sta; + u32 reserved5[13]; + u32 i2c_dbtool_misc; + u32 md_sleep_ctrl_mask; + u32 pmicw_clock_ctrl; + u32 reserved6[5]; + u32 infra_globalcon_rst0_set; + u32 infra_globalcon_rst0_clr; + u32 infra_globalcon_rst0_sta; + u32 reserved7[1]; + u32 infra_globalcon_rst1_set; + u32 infra_globalcon_rst1_clr; + u32 infra_globalcon_rst1_sta; + u32 reserved8[1]; + u32 infra_globalcon_rst2_set; + u32 infra_globalcon_rst2_clr; + u32 infra_globalcon_rst2_sta; + u32 reserved9[1]; + u32 infra_globalcon_rst3_set; + u32 infra_globalcon_rst3_clr; + u32 infra_globalcon_rst3_sta; + u32 reserved10[41]; + u32 infra_topaxi_si0_ctl; + u32 infra_topaxi_si1_ctl; + u32 infra_topaxi_mdbus_ctl; + u32 infra_mci_si0_ctl; + u32 infra_mci_si1_ctl; + u32 infra_mci_si2_ctl; + u32 infra_mci_async_ctl; + u32 infra_mci_cg_mfg_sec_sta; + u32 infra_topaxi_protecten; + u32 infra_topaxi_protecten_sta0; + u32 infra_topaxi_protecten_sta1; + u32 infra_axi_aslice_ctrl; + u32 infra_apb_async_sta; + u32 infra_topaxi_si2_ctl; + u32 reserved11[1]; + u32 infra_topaxi_trans_limiter_1; + u32 infra_mci_trans_con_read; + u32 infra_mci_trans_con_write; + u32 infra_mci_id_remap_con; + u32 infra_mci_emi_trans_con; + u32 infra_topaxi_protecten_1; + u32 infra_topaxi_protecten_sta0_1; + u32 infra_topaxi_protecten_sta1_1; + u32 reserved12[1]; + u32 infra_topaxi_aslice_ctrl; + u32 infra_topaxi_protecten_2; + u32 infra_topaxi_protecten_sta0_2; + u32 infra_topaxi_protecten_sta1_2; + u32 infra_topaxi_mi_ctrl; + u32 infra_topaxi_cbip_aslice_ctrl; + u32 infra_topaxi_cbip_slice_ctrl; + u32 infra_top_master_sideband; + u32 reserved13[1]; + u32 infra_topaxi_trans_limiter; + u32 infra_topaxi_emi_gmc_l2c_ctrl; + u32 infra_topaxi_cbip_slice_ctrl_1; + u32 infra_mfg_slave_gals_ctrl; + u32 infra_mfg_master_m0_gals_ctrl; + u32 infra_mfg_master_m1_gals_ctrl; + u32 infra_top_master_sideband_1; + u32 infra_topaxi_protecten_set; + u32 infra_topaxi_protecten_clr; + u32 infra_topaxi_protecten_1_set; + u32 infra_topaxi_protecten_1_clr; + u32 infra_topaxi_protecten_2_set; + u32 infra_topaxi_protecten_2_clr; + u32 infra_topaxi_protecten_3_set; + u32 infra_topaxi_protecten_3_clr; + u32 infra_topaxi_protecten_3; + u32 infra_topaxi_protecten_sta0_3; + u32 infra_topaxi_protecten_sta1_3; + u32 reserved14[12]; + u32 infra_topaxi_bus_dbg_con_a0; + u32 md1_bank0_map0; + u32 md1_bank0_map1; + u32 md1_bank0_map2; + u32 md1_bank0_map3; + u32 md1_bank1_map0; + u32 md1_bank1_map1; + u32 md1_bank1_map2; + u32 md1_bank1_map3; + u32 md1_bank4_map0; + u32 md1_bank4_map1; + u32 md1_bank4_map2; + u32 md1_bank4_map3; + u32 md2_bank0_map0; + u32 md2_bank0_map1; + u32 md2_bank0_map2; + u32 md2_bank0_map3; + u32 reserved15[4]; + u32 md2_bank4_map0; + u32 md2_bank4_map1; + u32 md2_bank4_map2; + u32 md2_bank4_map3; + u32 c2k_config; + u32 c2k_status; + u32 c2k_spm_ctrl; + u32 reserved16[1]; + u32 ap2md_dummy; + u32 reserved17[3]; + u32 conn_map0; + u32 cldma_map0; + u32 conn_map1; + u32 conn_bus_con; + u32 mcusys_dfd_map; + u32 reserved18[1]; + u32 conn_map3; + u32 conn_map4; + u32 reserved19[24]; + u32 peri_cci_sideband_con; + u32 mfg_cci_sideband_con; + u32 reserved20[2]; + u32 infra_pwm_cksw_ctrl; + u32 reserved21[59]; + u32 infra_ao_dbg_con0; + u32 infra_ao_dbg_con1; + u32 infra_ao_dbg_con2; + u32 infra_ao_dbg_con3; + u32 md_dbg_ck_con; + u32 reserved22[59]; + u32 mfg_misc_con; + u32 reserved23[62]; + u32 infra_msdc_con; + u32 infra_rsvd0; + u32 infra_rsvd1; + u32 infra_rsvd2; + u32 infra_rsvd3; + u32 infra_rsvd4; + u32 infra_rsvd5; + u32 infra_iommu_en; + u32 reserved24[89]; + u32 md1_sbc_key0; + u32 md1_sbc_key1; + u32 md1_sbc_key2; + u32 md1_sbc_key3; + u32 md1_sbc_key4; + u32 md1_sbc_key5; + u32 md1_sbc_key6; + u32 md1_sbc_key7; + u32 md1_sbc_key_lock; + u32 reserved25[1]; + u32 md1_misc_lock; + u32 md1_misc; + u32 c2k_sbc_key0; + u32 c2k_sbc_key1; + u32 c2k_sbc_key2; + u32 c2k_sbc_key3; + u32 c2k_sbc_key4; + u32 c2k_sbc_key5; + u32 c2k_sbc_key6; + u32 c2k_sbc_key7; + u32 c2k_sbc_key_lock; + u32 reserved26[11]; + u32 infra_bonding; + u32 subsys_pdn_nohang_dis0; + u32 subsys_pdn_nohang_dis1; + u32 reserved27[61]; + u32 infra_ao_scpsys_apb_async_sta; + u32 infra_ao_md32_tx_apb_async_sta; + u32 infra_ao_md32_rx_apb_async_sta; + u32 infra_ao_cksys_apb_async_sta; + u32 infra_ao_pmic_wrap_tx_apb_async_sta; + u32 infra_ao_pmif_spmi_tx_apb_async_sta; + u32 infra_ao_spmi_mst_tx_apb_async_sta; + u32 infra_ao_infra0_iommu_apb_async_sta; + u32 infra_ao_infra1_iommu_apb_async_sta; + u32 reserved28[6]; + u32 infra_ao_mcu_pwr_mask; + u32 reserved29[48]; + u32 pll_ulposc_con0; + u32 pll_ulposc_con1; + u32 reserved30[2]; + u32 pll_auxadc_con0; + u32 scp_infra_irq_set; + u32 scp_infra_irq_clr; + u32 scp_infra_ctrl; + u32 conn2infra_gals_dbg; + u32 infra_infra2adsp_axi_gals_debug; + u32 infra_adsp2infra_axi_gals_debug; + u32 infra_adsp2emi_axi_gals_debug; + u32 nna0_1_emi_axi_gals_debug; + u32 nna2_emi_axi_gals_debug; + u32 nn2infra_axi_gals_debug; + u32 infra2nna_axi_gals_debug; + u32 reserved31[48]; + u32 cldma_ctrl; + u32 reserved32[3]; + u32 rg_ccif4_md_pwr_flag; + u32 rg_ccif4_con_pwr_flag; + u32 rd_ccif4_cpu_pwr_flag; + u32 reserved33[1]; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0; + u32 reserved34[1]; + u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0; + u32 infra_ipsys_s_bus_u_si0_ctrl_0; + u32 infra_ipsys_s_bus_u_si0_ctrl_1; + u32 infra_ipsys_s_bus_u_si0_ctrl_2; + u32 infra_ipsys_s_bus_u_si0_ctrl_3; + u32 infra_ipsys_s_bus_u_si0_ctrl_4; + u32 infra_ipsys_s_bus_u_si0_ctrl_5; + u32 reserved35[40]; + u32 infrabus_dbg0; + u32 infrabus_dbg1; + u32 infrabus_dbg2; + u32 infrabus_dbg3; + u32 infrabus_dbg4; + u32 infrabus_dbg5; + u32 infrabus_dbg6; + u32 infrabus_dbg7; + u32 infrabus_dbg8; + u32 infrabus_dbg9; + u32 infrabus_dbg10; + u32 infrabus_dbg11; + u32 infrabus_dbg12; + u32 infrabus_dbg13; + u32 infrabus_dbg14; + u32 infrabus_dbg15; + u32 infrabus_dbg16; + u32 reserved36[111]; + u32 infra_misc; + u32 infra_acp; + u32 misc_config; + u32 infra_misc2; + u32 mdsys_misc_con; + u32 reserved37[12]; + u32 nna_infra_gals_ctrl; + u32 nna_emi_gals_ctrl; + u32 infra_adsp_infra_gals_ctrl; + u32 infra_adsp_emi_gals_ctrl; + u32 reserved38[11]; + u32 infra_ao_sec_con; + u32 infra_ao_sec_cg_con0; + u32 infra_ao_sec_cg_con1; + u32 infra_ao_sec_rst_con0; + u32 infra_ao_sec_rst_con1; + u32 infra_ao_sec_rst_con2; + u32 dxcc_dcu_en_lock; + u32 infra_ao_sec_cg_con2; + u32 infra_ao_sec_rst_con3; + u32 infra_ao_sec_cg_con3; + u32 reserved39[2]; + u32 infra_ao_sec_hyp; + u32 infra_mcu2emi_slice; + u32 infra_ao_sec_mfg_hyp; +}; + +check_member(mt8186_infracfg_ao_regs, infra_globalcon_dcmctl, 0x50); +check_member(mt8186_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x70); +check_member(mt8186_infracfg_ao_regs, peri_bus_dcm_ctrl, 0x74); +check_member(mt8186_infracfg_ao_regs, mem_dcm_ctrl, 0x78); +check_member(mt8186_infracfg_ao_regs, dfs_mem_dcm_ctrl, 0x7c); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_set, 0x80); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_clr, 0x84); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_set, 0x88); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_clr, 0x8c); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_sta, 0x90); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_sta, 0x94); +check_member(mt8186_infracfg_ao_regs, module_clk_sel, 0x98); +check_member(mt8186_infracfg_ao_regs, mem_cg_ctrl, 0x9c); +check_member(mt8186_infracfg_ao_regs, p2p_rx_clk_on, 0xa0); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_set, 0xa4); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_clr, 0xa8); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_sta, 0xac); +check_member(mt8186_infracfg_ao_regs, dramc_wbr, 0xb4); +check_member(mt8186_infracfg_ao_regs, ddr_en_mask, 0xb8); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_set, 0xc0); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_clr, 0xc4); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_sta, 0xc8); +check_member(mt8186_infracfg_ao_regs, i2c_dbtool_misc, 0x100); +check_member(mt8186_infracfg_ao_regs, md_sleep_ctrl_mask, 0x104); +check_member(mt8186_infracfg_ao_regs, pmicw_clock_ctrl, 0x108); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_set, 0x120); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_clr, 0x124); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_sta, 0x128); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_set, 0x130); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_clr, 0x134); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_sta, 0x138); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_set, 0x140); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_clr, 0x144); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_sta, 0x148); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_set, 0x150); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_clr, 0x154); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_sta, 0x158); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_si0_ctl, 0x200); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_si1_ctl, 0x204); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_mdbus_ctl, 0x208); +check_member(mt8186_infracfg_ao_regs, infra_mci_si0_ctl, 0x20c); +check_member(mt8186_infracfg_ao_regs, infra_mci_si1_ctl, 0x210); +check_member(mt8186_infracfg_ao_regs, infra_mci_si2_ctl, 0x214); +check_member(mt8186_infracfg_ao_regs, infra_mci_async_ctl, 0x218); +check_member(mt8186_infracfg_ao_regs, infra_mci_cg_mfg_sec_sta, 0x21c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten, 0x220); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0, 0x224); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1, 0x228); +check_member(mt8186_infracfg_ao_regs, infra_axi_aslice_ctrl, 0x22c); +check_member(mt8186_infracfg_ao_regs, infra_apb_async_sta, 0x230); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_si2_ctl, 0x234); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_trans_limiter_1, 0x23c); +check_member(mt8186_infracfg_ao_regs, infra_mci_trans_con_read, 0x240); +check_member(mt8186_infracfg_ao_regs, infra_mci_trans_con_write, 0x244); +check_member(mt8186_infracfg_ao_regs, infra_mci_id_remap_con, 0x248); +check_member(mt8186_infracfg_ao_regs, infra_mci_emi_trans_con, 0x24c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1, 0x250); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_1, 0x254); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_1, 0x258); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_aslice_ctrl, 0x260); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2, 0x264); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_2, 0x268); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_2, 0x26c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_mi_ctrl, 0x270); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_aslice_ctrl, 0x274); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_slice_ctrl, 0x278); +check_member(mt8186_infracfg_ao_regs, infra_top_master_sideband, 0x27c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_trans_limiter, 0x284); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_emi_gmc_l2c_ctrl, 0x288); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_slice_ctrl_1, 0x28c); +check_member(mt8186_infracfg_ao_regs, infra_mfg_slave_gals_ctrl, 0x290); +check_member(mt8186_infracfg_ao_regs, infra_mfg_master_m0_gals_ctrl, 0x294); +check_member(mt8186_infracfg_ao_regs, infra_mfg_master_m1_gals_ctrl, 0x298); +check_member(mt8186_infracfg_ao_regs, infra_top_master_sideband_1, 0x29c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_set, 0x2a0); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_clr, 0x2a4); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1_set, 0x2a8); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1_clr, 0x2ac); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2_set, 0x2b0); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2_clr, 0x2b4); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3_set, 0x2b8); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3_clr, 0x2bc); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3, 0x2c0); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_3, 0x2c4); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_3, 0x2c8); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_bus_dbg_con_a0, 0x2fc); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map0, 0x300); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map1, 0x304); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map2, 0x308); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map3, 0x30c); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map0, 0x310); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map1, 0x314); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map2, 0x318); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map3, 0x31c); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map0, 0x320); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map1, 0x324); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map2, 0x328); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map3, 0x32c); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map0, 0x330); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map1, 0x334); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map2, 0x338); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map3, 0x33c); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map0, 0x350); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map1, 0x354); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map2, 0x358); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map3, 0x35c); +check_member(mt8186_infracfg_ao_regs, c2k_config, 0x360); +check_member(mt8186_infracfg_ao_regs, c2k_status, 0x364); +check_member(mt8186_infracfg_ao_regs, c2k_spm_ctrl, 0x368); +check_member(mt8186_infracfg_ao_regs, ap2md_dummy, 0x370); +check_member(mt8186_infracfg_ao_regs, conn_map0, 0x380); +check_member(mt8186_infracfg_ao_regs, cldma_map0, 0x384); +check_member(mt8186_infracfg_ao_regs, conn_map1, 0x388); +check_member(mt8186_infracfg_ao_regs, conn_bus_con, 0x38c); +check_member(mt8186_infracfg_ao_regs, mcusys_dfd_map, 0x390); +check_member(mt8186_infracfg_ao_regs, conn_map3, 0x398); +check_member(mt8186_infracfg_ao_regs, conn_map4, 0x39c); +check_member(mt8186_infracfg_ao_regs, peri_cci_sideband_con, 0x400); +check_member(mt8186_infracfg_ao_regs, mfg_cci_sideband_con, 0x404); +check_member(mt8186_infracfg_ao_regs, infra_pwm_cksw_ctrl, 0x410); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con0, 0x500); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con1, 0x504); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con2, 0x508); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con3, 0x50c); +check_member(mt8186_infracfg_ao_regs, md_dbg_ck_con, 0x510); +check_member(mt8186_infracfg_ao_regs, mfg_misc_con, 0x600); +check_member(mt8186_infracfg_ao_regs, infra_msdc_con, 0x6fc); +check_member(mt8186_infracfg_ao_regs, infra_rsvd0, 0x700); +check_member(mt8186_infracfg_ao_regs, infra_rsvd1, 0x704); +check_member(mt8186_infracfg_ao_regs, infra_rsvd2, 0x708); +check_member(mt8186_infracfg_ao_regs, infra_rsvd3, 0x70c); +check_member(mt8186_infracfg_ao_regs, infra_rsvd4, 0x710); +check_member(mt8186_infracfg_ao_regs, infra_rsvd5, 0x714); +check_member(mt8186_infracfg_ao_regs, infra_iommu_en, 0x718); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key0, 0x880); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key1, 0x884); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key2, 0x888); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key3, 0x88c); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key4, 0x890); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key5, 0x894); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key6, 0x898); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key7, 0x89c); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key_lock, 0x8a0); +check_member(mt8186_infracfg_ao_regs, md1_misc_lock, 0x8a8); +check_member(mt8186_infracfg_ao_regs, md1_misc, 0x8ac); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key0, 0x8b0); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key1, 0x8b4); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key2, 0x8b8); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key3, 0x8bc); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key4, 0x8c0); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key5, 0x8c4); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key6, 0x8c8); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key7, 0x8cc); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key_lock, 0x8d0); +check_member(mt8186_infracfg_ao_regs, infra_bonding, 0x900); +check_member(mt8186_infracfg_ao_regs, subsys_pdn_nohang_dis0, 0x904); +check_member(mt8186_infracfg_ao_regs, subsys_pdn_nohang_dis1, 0x908); +check_member(mt8186_infracfg_ao_regs, infra_ao_scpsys_apb_async_sta, 0xa00); +check_member(mt8186_infracfg_ao_regs, infra_ao_md32_tx_apb_async_sta, 0xa04); +check_member(mt8186_infracfg_ao_regs, infra_ao_md32_rx_apb_async_sta, 0xa08); +check_member(mt8186_infracfg_ao_regs, infra_ao_cksys_apb_async_sta, 0xa0c); +check_member(mt8186_infracfg_ao_regs, infra_ao_pmic_wrap_tx_apb_async_sta, 0xa10); +check_member(mt8186_infracfg_ao_regs, infra_ao_pmif_spmi_tx_apb_async_sta, 0xa14); +check_member(mt8186_infracfg_ao_regs, infra_ao_spmi_mst_tx_apb_async_sta, 0xa18); +check_member(mt8186_infracfg_ao_regs, infra_ao_infra0_iommu_apb_async_sta, 0xa1c); +check_member(mt8186_infracfg_ao_regs, infra_ao_infra1_iommu_apb_async_sta, 0xa20); +check_member(mt8186_infracfg_ao_regs, infra_ao_mcu_pwr_mask, 0xa3c); +check_member(mt8186_infracfg_ao_regs, pll_ulposc_con0, 0xb00); +check_member(mt8186_infracfg_ao_regs, pll_ulposc_con1, 0xb04); +check_member(mt8186_infracfg_ao_regs, pll_auxadc_con0, 0xb10); +check_member(mt8186_infracfg_ao_regs, scp_infra_irq_set, 0xb14); +check_member(mt8186_infracfg_ao_regs, scp_infra_irq_clr, 0xb18); +check_member(mt8186_infracfg_ao_regs, scp_infra_ctrl, 0xb1c); +check_member(mt8186_infracfg_ao_regs, conn2infra_gals_dbg, 0xb20); +check_member(mt8186_infracfg_ao_regs, infra_infra2adsp_axi_gals_debug, 0xb24); +check_member(mt8186_infracfg_ao_regs, infra_adsp2infra_axi_gals_debug, 0xb28); +check_member(mt8186_infracfg_ao_regs, infra_adsp2emi_axi_gals_debug, 0xb2c); +check_member(mt8186_infracfg_ao_regs, nna0_1_emi_axi_gals_debug, 0xb30); +check_member(mt8186_infracfg_ao_regs, nna2_emi_axi_gals_debug, 0xb34); +check_member(mt8186_infracfg_ao_regs, nn2infra_axi_gals_debug, 0xb38); +check_member(mt8186_infracfg_ao_regs, infra2nna_axi_gals_debug, 0xb3c); +check_member(mt8186_infracfg_ao_regs, cldma_ctrl, 0xc00); +check_member(mt8186_infracfg_ao_regs, rg_ccif4_md_pwr_flag, 0xc10); +check_member(mt8186_infracfg_ao_regs, rg_ccif4_con_pwr_flag, 0xc14); +check_member(mt8186_infracfg_ao_regs, rd_ccif4_cpu_pwr_flag, 0xc18); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0, 0xc20); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0, 0xc24); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0, 0xc28); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0, 0xc2c); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0, 0xc30); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0, 0xc34); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0, 0xc38); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0, 0xc40); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0, 0xc44); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_0, 0xc48); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_1, 0xc4c); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_2, 0xc50); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_3, 0xc54); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_4, 0xc58); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_5, 0xc5c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg0, 0xd00); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg1, 0xd04); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg2, 0xd08); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg3, 0xd0c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg4, 0xd10); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg5, 0xd14); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg6, 0xd18); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg7, 0xd1c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg8, 0xd20); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg9, 0xd24); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg10, 0xd28); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg11, 0xd2c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg12, 0xd30); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg13, 0xd34); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg14, 0xd38); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg15, 0xd3c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg16, 0xd40); +check_member(mt8186_infracfg_ao_regs, infra_misc, 0xf00); +check_member(mt8186_infracfg_ao_regs, infra_acp, 0xf04); +check_member(mt8186_infracfg_ao_regs, misc_config, 0xf08); +check_member(mt8186_infracfg_ao_regs, infra_misc2, 0xf0c); +check_member(mt8186_infracfg_ao_regs, mdsys_misc_con, 0xf10); +check_member(mt8186_infracfg_ao_regs, nna_infra_gals_ctrl, 0xf44); +check_member(mt8186_infracfg_ao_regs, nna_emi_gals_ctrl, 0xf48); +check_member(mt8186_infracfg_ao_regs, infra_adsp_infra_gals_ctrl, 0xf4c); +check_member(mt8186_infracfg_ao_regs, infra_adsp_emi_gals_ctrl, 0xf50); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_con, 0xf80); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con0, 0xf84); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con1, 0xf88); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con0, 0xf8c); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con1, 0xf90); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con2, 0xf94); +check_member(mt8186_infracfg_ao_regs, dxcc_dcu_en_lock, 0xf98); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con2, 0xf9c); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con3, 0xfa0); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con3, 0xfa4); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_hyp, 0xfb0); +check_member(mt8186_infracfg_ao_regs, infra_mcu2emi_slice, 0xfb4); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_mfg_hyp, 0xfb8); + +static struct mt8186_infracfg_ao_regs *const mt8186_infracfg_ao = + (void *)INFRACFG_AO_BASE; + +#endif /* SOC_MEDIATEK_MT8186_INFRACFG_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/mcucfg.h b/src/soc/mediatek/mt8186/include/soc/mcucfg.h new file mode 100644 index 000000000000..241840696264 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/mcucfg.h @@ -0,0 +1,947 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.1 + */ + +#ifndef SOC_MEDIATEK_MT8186_MCUCFG_H +#define SOC_MEDIATEK_MT8186_MCUCFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8186_mcucfg_regs { + u32 reserved1[2]; + u32 mbista_mcsi_sf1_con; + u32 mbista_mcsi_sf1_result; + u32 mbista_mcsi_sf2_con; + u32 mbista_mcsi_sf2_result; + u32 mbista_etb_con; + u32 mbista_etb_result; + u32 mbista_rstb; + u32 mbista_all_result; + u32 reserved2[2]; + u32 mbist_trigger_mux_ctl; + u32 reserved3[3]; + u32 dfd_ctrl; + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u32 reserved4[5]; + u32 mp_top_dbg_mon_sel; + u32 mp_top_dbg_mon; + u32 mp0_dbg_mon_sel; + u32 mp0_dbg_mon; + u32 reserved5[8]; + u32 l2_parity_clr; + u32 l2_parity_info1_cpu0; + u32 l2_parity_info2_cpu0; + u32 l2_parity_info1_cpu1; + u32 l2_parity_info2_cpu1; + u32 l2_parity_info1_cpu2; + u32 l2_parity_info2_cpu2; + u32 l2_parity_info1_cpu3; + u32 l2_parity_info2_cpu3; + u32 l2_parity_info1_cpu4; + u32 l2_parity_info2_cpu4; + u32 l2_parity_info1_cpu5; + u32 l2_parity_info2_cpu5; + u32 l2_parity_info1_cpu6; + u32 l2_parity_info2_cpu6; + u32 l2_parity_info1_cpu7; + u32 l2_parity_info2_cpu7; + u32 reserved6[10]; + u32 apmcu2emi_early_cke_ctl; + u32 cci_tra_cfg0; + u32 reserved7[4]; + u32 cci_tra_cfg5; + u32 cci_tra_cfg6; + u32 cci_tra_cfg7; + u32 cci_tra_cfg8; + u32 cci_tra_cfg9; + u32 cci_tra_cfg10; + u32 cci_tra_cfg11; + u32 cci_tra_cfg12; + u32 reserved8[51]; + u32 cci_m0_tra; + u32 cci_m1_tra; + u32 cci_m2_tra; + u32 reserved9[5]; + u32 cci_s1_tra; + u32 cci_s2_tra; + u32 cci_s3_tra; + u32 cci_s4_tra; + u32 reserved10[4]; + u32 cci_m0_tra_latch; + u32 cci_m1_tra_latch; + u32 cci_m2_tra_latch; + u32 reserved11[5]; + u32 cci_s1_tra_latch; + u32 cci_s2_tra_latch; + u32 cci_s3_tra_latch; + u32 cci_s4_tra_latch; + u32 reserved12[20]; + u32 cci_m0_if; + u32 cci_m1_if; + u32 cci_m2_if; + u32 reserved13[5]; + u32 cci_s1_if; + u32 cci_s2_if; + u32 cci_s3_if; + u32 cci_s4_if; + u32 reserved14[4]; + u32 cci_top_if; + u32 reserved15[7]; + u32 cci_m0_if_latch; + u32 cci_m1_if_latch; + u32 cci_m2_if_latch; + u32 reserved16[5]; + u32 cci_s1_if_latch; + u32 cci_s2_if_latch; + u32 cci_s3_if_latch; + u32 cci_s4_if_latch; + u32 reserved17[4]; + u32 cci_top_if_latch; + u32 reserved18[39]; + u32 l3c_share_status0; + u32 l3c_share_status1; + u32 l3c_share_status2; + u32 reserved19[1]; + u32 mp0_cpu0_dc_age; + u32 mp0_cpu1_dc_age; + u32 mp0_cpu2_dc_age; + u32 mp0_cpu3_dc_age; + u32 mp0_cpu4_dc_age; + u32 mp0_cpu5_dc_age; + u32 mp0_cpu6_dc_age; + u32 mp0_cpu7_dc_age; + u32 reserved20[52]; + u32 mp0_cpu0_nonwfx_ctrl; + u32 mp0_cpu0_nonwfx_cnt; + u32 mp0_cpu1_nonwfx_ctrl; + u32 mp0_cpu1_nonwfx_cnt; + u32 mp0_cpu2_nonwfx_ctrl; + u32 mp0_cpu2_nonwfx_cnt; + u32 mp0_cpu3_nonwfx_ctrl; + u32 mp0_cpu3_nonwfx_cnt; + u32 mp0_cpu4_nonwfx_ctrl; + u32 mp0_cpu4_nonwfx_cnt; + u32 mp0_cpu5_nonwfx_ctrl; + u32 mp0_cpu5_nonwfx_cnt; + u32 mp0_cpu6_nonwfx_ctrl; + u32 mp0_cpu6_nonwfx_cnt; + u32 mp0_cpu7_nonwfx_ctrl; + u32 mp0_cpu7_nonwfx_cnt; + u32 reserved21[48]; + u32 mp0_ses_apb_trig; + u32 reserved22[3]; + u32 wfx_ret_met_dbc_sel; + u32 reserved23[3]; + u32 adb_bist_cfg1; + u32 adb_bist_cfg2_md; + u32 adb_bist_cfg3_go; + u32 adb_bist_done; + u32 adb_bist_pass; + u32 reserved24[1667]; + u32 dfd_internal_ctl; + u32 dfd_internal_counter; + u32 dfd_internal_pwr_on; + u32 dfd_internal_chain_legth_0; + u32 dfd_internal_shift_clk_ratio; + u32 dfd_internal_counter_return; + u32 dfd_internal_sram_access; + u32 dfd_internal_chain_length_1; + u32 dfd_internal_chain_length_2; + u32 dfd_internal_chain_length_3; + u32 dfd_internal_test_so_0; + u32 dfd_internal_test_so_1; + u32 dfd_internal_num_of_test_so_gp; + u32 dfd_internal_test_so_over_64; + u32 dfd_internal_mask_out; + u32 dfd_internal_sw_ns_trigger; + u32 dfd_internal_mcsi; + u32 dfd_internal_mcsi_sel_status; + u32 dfd_v30_ctl; + u32 dfd_v30_base_addr; + u32 dfd_power_ctl; + u32 dfd_reset_on; + u32 dfd_test_si_0; + u32 dfd_test_si_1; + u32 dfd_status_clean; + u32 dfd_status_return; + u32 reserved25[21]; + u32 dfd_hw_trigger_mask; + u32 reserved26[64]; + u32 mcusys_par_wrap_dbg_mon_sel; + u32 mcusys_par_wrap_dbg_mon; + u32 mcusys_pinmux; + u32 reserved27[1]; + u32 l3c_share_cfg0; + u32 l3c_share_cfg1; + u32 l3c_share_cfg2; + u32 reserved28[1]; + u32 udi_cfg0; + u32 udi_cfg1; + u32 reserved29[2]; + u32 mcusys_core_status; + u32 reserved30[11]; + u32 mcusys_base; + u32 l3c_sram_base; + u32 gic_periph_base; + u32 cci_periph_base; + u32 cci_periph_infra_base; + u32 dfd_sram_base; + u32 l3c_mm_sram_base; + u32 reserved31[9]; + u32 cpu_plldiv_cfg0; + u32 cpu_plldiv_cfg1; + u32 cpu_plldiv_cfg2; + u32 reserved32[13]; + u32 bus_plldiv_cfg; + u32 reserved33[3]; + u32 plldiv_ctl0; + u32 reserved34[3]; + u32 mcsi_ram_delsel0; + u32 mcsi_ram_delsel1; + u32 reserved35[6]; + u32 etb_ram_delsel0; + u32 reserved36[23]; + u32 etb_cfg0; + u32 reserved37[31]; + u32 cci_rgu; + u32 reserved38[3]; + u32 mcsi_cfg0; + u32 mcsi_cfg1; + u32 mcsi_cfg2; + u32 mcsi_cfg3; + u32 mcsi_cfg4; + u32 reserved39[7]; + u32 mcsic_dcm0; + u32 mcsic_dcm1; + u32 reserved40[46]; + u32 mp_adb_dcm_cfg0; + u32 reserved41[1]; + u32 mp_adb_dcm_cfg2; + u32 reserved42[1]; + u32 mp_adb_dcm_cfg4; + u32 reserved43[1]; + u32 mp_misc_dcm_cfg0; + u32 reserved44[9]; + u32 etb_ck_ctl; + u32 reserved45[15]; + u32 dcc_cpu_con0; + u32 dcc_cpu_con1; + u32 dcc_cpu_con2; + u32 reserved46[5]; + u32 dcc_bus_con0; + u32 reserved47[7]; + u32 mcusys_dcm_cfg0; + u32 reserved48[15]; + u32 sec_pol_ctl_en0; + u32 sec_pol_ctl_en1; + u32 sec_pol_ctl_en2; + u32 sec_pol_ctl_en3; + u32 sec_pol_ctl_en4; + u32 sec_pol_ctl_en5; + u32 sec_pol_ctl_en6; + u32 sec_pol_ctl_en7; + u32 sec_pol_ctl_en8; + u32 sec_pol_ctl_en9; + u32 sec_pol_ctl_en10; + u32 sec_pol_ctl_en11; + u32 sec_pol_ctl_en12; + u32 sec_pol_ctl_en13; + u32 sec_pol_ctl_en14; + u32 sec_pol_ctl_en15; + u32 sec_pol_ctl_en16; + u32 sec_pol_ctl_en17; + u32 sec_pol_ctl_en18; + u32 sec_pol_ctl_en19; + u32 int_pol_ctl0; + u32 int_pol_ctl1; + u32 int_pol_ctl2; + u32 int_pol_ctl3; + u32 int_pol_ctl4; + u32 int_pol_ctl5; + u32 int_pol_ctl6; + u32 int_pol_ctl7; + u32 int_pol_ctl8; + u32 int_pol_ctl9; + u32 int_pol_ctl10; + u32 int_pol_ctl11; + u32 int_pol_ctl12; + u32 int_pol_ctl13; + u32 int_pol_ctl14; + u32 int_pol_ctl15; + u32 int_pol_ctl16; + u32 int_pol_ctl17; + u32 int_pol_ctl18; + u32 int_pol_ctl19; + u32 int_msk_ctl0; + u32 int_msk_ctl1; + u32 int_msk_ctl2; + u32 int_msk_ctl3; + u32 int_msk_ctl4; + u32 int_msk_ctl5; + u32 int_msk_ctl6; + u32 int_msk_ctl7; + u32 int_msk_ctl8; + u32 int_msk_ctl9; + u32 int_msk_ctl10; + u32 int_msk_ctl11; + u32 int_msk_ctl12; + u32 int_msk_ctl13; + u32 int_msk_ctl14; + u32 int_msk_ctl15; + u32 int_msk_ctl16; + u32 int_msk_ctl17; + u32 int_msk_ctl18; + u32 int_msk_ctl19; + u32 reserved49[1]; + u32 int_msk_ctl_all; + u32 int_cfg_indirect_access; + u32 int_cfg_direct_access_en; + u32 fcm_spmc_sw_cfg1; + u32 fcm_spmc_sw_cfg2; + u32 fcm_spmc_wait_cfg; + u32 fcm_spmc_sw_pchannel; + u32 fcm_spmc_pwr_status; + u32 fcm_spmc_off_thres; + u32 fcm_spmc_wdt_latch_info; + u32 reserved50[9]; + u32 mcusys_spmc_sw_cfg; + u32 mcusys_spmc_wait_cfg; + u32 mcusys_spmc_pwr_status; + u32 reserved51[45]; + u32 cpc_pllbuck_req_ctrl; + u32 mcusys_pwr_ctrl; + u32 cpusys_pwr_ctrl; + u32 sw_gic_wakeup_req; + u32 cpc_pllbuck_arb_weight; + u32 cpc_flow_ctrl_cfg; + u32 cpc_last_core_req; + u32 cpc_cpusys_last_core_resp; + u32 reserved52[1]; + u32 cpc_mcusys_last_core_resp; + u32 cpc_pwr_on_mask; + u32 reserved53[5]; + u32 cpc_spmc_pwr_status; + u32 cpc_core_cur_fsm; + u32 cpc_cpusys_mcusys_cur_fsm; + u32 cpc_wakeup_req; + u32 reserved54[3]; + u32 cpc_turbo_ctrl; + u32 cpc_turbo_gp0_ctrl; + u32 cpc_turbo_gp1_ctrl; + u32 cpc_turbo_gp2_ctrl; + u32 cpc_turbo_pwr_on_mask; + u32 cpc_turbo_gp0_req; + u32 cpc_turbo_gp1_req; + u32 cpc_turbo_gp2_req; + u32 reserved55[1]; + u32 cpc_turbo_gp0_resp; + u32 cpc_turbo_gp1_resp; + u32 cpc_turbo_gp2_resp; + u32 cpc_coh_block_thres; + u32 cpc_int_status; + u32 cpc_int_enable; + u32 pllbuck_group_func; + u32 cpc_dcm_enable; + u32 cpc_pllbuck_state; + u32 cpc_cpu_on_sw_hint; + u32 cpc_cpu_on_sw_hint_set; + u32 cpc_cpu_on_sw_hint_clear; + u32 reserved56[20]; + u32 emi_wfifo; + u32 axi1to4_cfg; + u32 reserved57[1]; + u32 emi_adb_edge_sel; + u32 reserved58[4]; + u32 sclk_cfg_slow_down_ck; + u32 reserved59[27]; + u32 mcusys_dbg_mon_sel; + u32 mcusys_dbg_mon; + u32 reserved60[58]; + u32 gic_acao_ctl0; + u32 gic_acao_ctl1; + u32 gic_acao_ctl2; + u32 reserved61[29]; + u32 spmc_dbg_setting; + u32 kernel_base_l; + u32 kernel_base_h; + u32 systime_base_l; + u32 systime_base_h; + u32 trace_data_selection; + u32 reserved62[2]; + u32 trace_data_entry0_l; + u32 trace_data_entry0_h; + u32 trace_data_entry1_l; + u32 trace_data_entry1_h; + u32 trace_data_entry2_l; + u32 trace_data_entry2_h; + u32 trace_data_entry3_l; + u32 trace_data_entry3_h; + u32 cpu0_on_off_latency; + u32 cpu1_on_off_latency; + u32 cpu2_on_off_latency; + u32 cpu3_on_off_latency; + u32 cpu4_on_off_latency; + u32 cpu5_on_off_latency; + u32 cpu6_on_off_latency; + u32 cpu7_on_off_latency; + u32 cluster_off_latency; + u32 cluster_on_latency; + u32 mcusys_on_off_latency; + u32 reserved63[1]; + u32 cluster_off_dormant_counter; + u32 cluster_off_dormant_counter_clear; + u32 reserved64[2]; + u32 cpc_wdt_latch_info1; + u32 cpc_wdt_latch_info2; + u32 cpc_wdt_latch_info3; + u32 cpc_wdt_latch_info4; + u32 cpc_wdt_latch_info5; + u32 cpc_pmu_ctrl; + u32 cpc_pmu_cnt_clr; + u32 cpc_pmu_cnt0; + u32 reserved65[88]; + u32 ildo_vproc2_en; + u32 reserved66[63]; + u32 pikachu_event; + u32 pikachu_status; + u32 reserved67[126]; + u32 cpu0_drcc_ao_config; + u32 reserved68[125]; + u32 cpu0_resereved_reg; + u32 cpu0_resereved_reg_rd; + u32 cpu1_drcc_ao_config; + u32 reserved69[125]; + u32 cpu1_resereved_reg; + u32 cpu1_resereved_reg_rd; + u32 cpu2_drcc_ao_config; + u32 reserved70[125]; + u32 cpu2_resereved_reg; + u32 cpu2_resereved_reg_rd; + u32 cpu3_drcc_ao_config; + u32 reserved71[125]; + u32 cpu3_resereved_reg; + u32 cpu3_resereved_reg_rd; + u32 cpu4_drcc_ao_config; + u32 reserved72[125]; + u32 cpu4_resereved_reg; + u32 cpu4_resereved_reg_rd; + u32 cpu5_drcc_ao_config; + u32 reserved73[125]; + u32 cpu5_resereved_reg; + u32 cpu5_resereved_reg_rd; + u32 cpu6_drcc_ao_config; + u32 reserved74[125]; + u32 cpu6_resereved_reg; + u32 cpu6_resereved_reg_rd; + u32 cpu7_drcc_ao_config; + u32 reserved75[125]; + u32 cpu7_resereved_reg; + u32 cpu7_resereved_reg_rd; + u32 reserved76[528]; + u32 mp0_l3_data_ram_delsel; + u32 mp0_l3_tag_ram_delsel; + u32 mp0_l3_victim_ram_delsel; + u32 mp0_l3_scu_sf_ram_delsel; + u32 reserved77[12]; + u32 mp0_dcm_cfg0; + u32 mp0_dcm_cfg1; + u32 mp0_dcm_cfg2; + u32 mp0_dcm_cfg3; + u32 mp0_dcm_cfg4; + u32 mp0_dcm_cfg5; + u32 mp0_dcm_cfg6; + u32 mp0_dcm_cfg7; + u32 mp0_dcm_cfg8; + u32 reserved78[7]; + u32 mp0_l3_cache_parity1; + u32 mp0_l3_cache_parity2; + u32 mp0_l3_cache_parity3; + u32 reserved79[1]; + u32 mp0_cluster_cfg0; + u32 reserved80[3]; + u32 mp0_cluster_cfg4; + u32 mp0_cluster_cfg5; + u32 mp0_cluster_cfg6; + u32 mp0_cluster_cfg7; + u32 reserved81[4]; + u32 mp0_cluster_cfg8; + u32 mp0_cluster_cfg9; + u32 mp0_cluster_cfg10; + u32 mp0_cluster_cfg11; + u32 mp0_cluster_cfg12; + u32 mp0_cluster_cfg13; + u32 mp0_cluster_cfg14; + u32 mp0_cluster_cfg15; + u32 mp0_cluster_cfg16; + u32 mp0_cluster_cfg17; + u32 mp0_cluster_cfg18; + u32 mp0_cluster_cfg19; + u32 mp0_cluster_cfg20; + u32 mp0_cluster_cfg21; + u32 mp0_cluster_cfg22; + u32 mp0_cluster_cfg23; + u32 reserved82[1]; + u32 mp0_victim_rd_mask; + u32 reserved83[174]; + u32 cpu_type0_spmc0_cfg; + u32 reserved84[7]; + u32 cpu_type0_ram_delsel0_cfg; + u32 cpu_type0_ram_delsel1_cfg; + u32 cpu_type0_ram_delsel2_cfg; + u32 reserved85[53]; + u32 cpu_type1_spmc0_cfg; + u32 reserved86[3]; + u32 cpu_type1_mpmmen; + u32 reserved87[3]; + u32 cpu_type1_ram_delsel0_cfg; + u32 cpu_type1_ram_delsel1_cfg; + u32 cpu_type1_ram_delsel2_cfg; + u32 reserved88[53]; + u32 plldiv_turbo; + u32 plldiv_percore_dfs_1; + u32 plldiv_percore_dfs_2; + u32 plldiv_imax_cg; + u32 plldiv_imax_int; + u32 plldiv_imax_detector; + u32 plldiv_little_reserved; + u32 plldiv_big_reserved; + u32 plldiv_bus_reserved; + u32 reserved89[3183]; + u32 mcusys_reserved_reg0; + u32 mcusys_reserved_reg1; + u32 mcusys_reserved_reg2; + u32 mcusys_reserved_reg3; + u32 mcusys_reserved_reg0_rd; + u32 mcusys_reserved_reg1_rd; + u32 mcusys_reserved_reg2_rd; + u32 mcusys_reserved_reg3_rd; +}; + +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf1_con, 0x8); +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf1_result, 0xc); +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf2_con, 0x10); +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf2_result, 0x14); +check_member(mt8186_mcucfg_regs, mbista_etb_con, 0x18); +check_member(mt8186_mcucfg_regs, mbista_etb_result, 0x1c); +check_member(mt8186_mcucfg_regs, mbista_rstb, 0x20); +check_member(mt8186_mcucfg_regs, mbista_all_result, 0x24); +check_member(mt8186_mcucfg_regs, mbist_trigger_mux_ctl, 0x30); +check_member(mt8186_mcucfg_regs, dfd_ctrl, 0x40); +check_member(mt8186_mcucfg_regs, dfd_cnt_l, 0x44); +check_member(mt8186_mcucfg_regs, dfd_cnt_h, 0x48); +check_member(mt8186_mcucfg_regs, mp_top_dbg_mon_sel, 0x60); +check_member(mt8186_mcucfg_regs, mp_top_dbg_mon, 0x64); +check_member(mt8186_mcucfg_regs, mp0_dbg_mon_sel, 0x68); +check_member(mt8186_mcucfg_regs, mp0_dbg_mon, 0x6c); +check_member(mt8186_mcucfg_regs, l2_parity_clr, 0x90); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu0, 0x94); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu0, 0x98); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu1, 0x9c); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu1, 0xa0); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu2, 0xa4); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu2, 0xa8); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu3, 0xac); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu3, 0xb0); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu4, 0xb4); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu4, 0xb8); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu5, 0xbc); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu5, 0xc0); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu6, 0xc4); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu6, 0xc8); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu7, 0xcc); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu7, 0xd0); +check_member(mt8186_mcucfg_regs, apmcu2emi_early_cke_ctl, 0xfc); +check_member(mt8186_mcucfg_regs, cci_tra_cfg0, 0x100); +check_member(mt8186_mcucfg_regs, cci_tra_cfg5, 0x114); +check_member(mt8186_mcucfg_regs, cci_tra_cfg6, 0x118); +check_member(mt8186_mcucfg_regs, cci_tra_cfg7, 0x11c); +check_member(mt8186_mcucfg_regs, cci_tra_cfg8, 0x120); +check_member(mt8186_mcucfg_regs, cci_tra_cfg9, 0x124); +check_member(mt8186_mcucfg_regs, cci_tra_cfg10, 0x128); +check_member(mt8186_mcucfg_regs, cci_tra_cfg11, 0x12c); +check_member(mt8186_mcucfg_regs, cci_tra_cfg12, 0x130); +check_member(mt8186_mcucfg_regs, cci_m0_tra, 0x200); +check_member(mt8186_mcucfg_regs, cci_m1_tra, 0x204); +check_member(mt8186_mcucfg_regs, cci_m2_tra, 0x208); +check_member(mt8186_mcucfg_regs, cci_s1_tra, 0x220); +check_member(mt8186_mcucfg_regs, cci_s2_tra, 0x224); +check_member(mt8186_mcucfg_regs, cci_s3_tra, 0x228); +check_member(mt8186_mcucfg_regs, cci_s4_tra, 0x22c); +check_member(mt8186_mcucfg_regs, cci_m0_tra_latch, 0x240); +check_member(mt8186_mcucfg_regs, cci_m1_tra_latch, 0x244); +check_member(mt8186_mcucfg_regs, cci_m2_tra_latch, 0x248); +check_member(mt8186_mcucfg_regs, cci_s1_tra_latch, 0x260); +check_member(mt8186_mcucfg_regs, cci_s2_tra_latch, 0x264); +check_member(mt8186_mcucfg_regs, cci_s3_tra_latch, 0x268); +check_member(mt8186_mcucfg_regs, cci_s4_tra_latch, 0x26c); +check_member(mt8186_mcucfg_regs, cci_m0_if, 0x2c0); +check_member(mt8186_mcucfg_regs, cci_m1_if, 0x2c4); +check_member(mt8186_mcucfg_regs, cci_m2_if, 0x2c8); +check_member(mt8186_mcucfg_regs, cci_s1_if, 0x2e0); +check_member(mt8186_mcucfg_regs, cci_s2_if, 0x2e4); +check_member(mt8186_mcucfg_regs, cci_s3_if, 0x2e8); +check_member(mt8186_mcucfg_regs, cci_s4_if, 0x2ec); +check_member(mt8186_mcucfg_regs, cci_top_if, 0x300); +check_member(mt8186_mcucfg_regs, cci_m0_if_latch, 0x320); +check_member(mt8186_mcucfg_regs, cci_m1_if_latch, 0x324); +check_member(mt8186_mcucfg_regs, cci_m2_if_latch, 0x328); +check_member(mt8186_mcucfg_regs, cci_s1_if_latch, 0x340); +check_member(mt8186_mcucfg_regs, cci_s2_if_latch, 0x344); +check_member(mt8186_mcucfg_regs, cci_s3_if_latch, 0x348); +check_member(mt8186_mcucfg_regs, cci_s4_if_latch, 0x34c); +check_member(mt8186_mcucfg_regs, cci_top_if_latch, 0x360); +check_member(mt8186_mcucfg_regs, l3c_share_status0, 0x400); +check_member(mt8186_mcucfg_regs, l3c_share_status1, 0x404); +check_member(mt8186_mcucfg_regs, l3c_share_status2, 0x408); +check_member(mt8186_mcucfg_regs, mp0_cpu0_dc_age, 0x410); +check_member(mt8186_mcucfg_regs, mp0_cpu1_dc_age, 0x414); +check_member(mt8186_mcucfg_regs, mp0_cpu2_dc_age, 0x418); +check_member(mt8186_mcucfg_regs, mp0_cpu3_dc_age, 0x41c); +check_member(mt8186_mcucfg_regs, mp0_cpu4_dc_age, 0x420); +check_member(mt8186_mcucfg_regs, mp0_cpu5_dc_age, 0x424); +check_member(mt8186_mcucfg_regs, mp0_cpu6_dc_age, 0x428); +check_member(mt8186_mcucfg_regs, mp0_cpu7_dc_age, 0x42c); +check_member(mt8186_mcucfg_regs, mp0_cpu0_nonwfx_ctrl, 0x500); +check_member(mt8186_mcucfg_regs, mp0_cpu0_nonwfx_cnt, 0x504); +check_member(mt8186_mcucfg_regs, mp0_cpu1_nonwfx_ctrl, 0x508); +check_member(mt8186_mcucfg_regs, mp0_cpu1_nonwfx_cnt, 0x50c); +check_member(mt8186_mcucfg_regs, mp0_cpu2_nonwfx_ctrl, 0x510); +check_member(mt8186_mcucfg_regs, mp0_cpu2_nonwfx_cnt, 0x514); +check_member(mt8186_mcucfg_regs, mp0_cpu3_nonwfx_ctrl, 0x518); +check_member(mt8186_mcucfg_regs, mp0_cpu3_nonwfx_cnt, 0x51c); +check_member(mt8186_mcucfg_regs, mp0_cpu4_nonwfx_ctrl, 0x520); +check_member(mt8186_mcucfg_regs, mp0_cpu4_nonwfx_cnt, 0x524); +check_member(mt8186_mcucfg_regs, mp0_cpu5_nonwfx_ctrl, 0x528); +check_member(mt8186_mcucfg_regs, mp0_cpu5_nonwfx_cnt, 0x52c); +check_member(mt8186_mcucfg_regs, mp0_cpu6_nonwfx_ctrl, 0x530); +check_member(mt8186_mcucfg_regs, mp0_cpu6_nonwfx_cnt, 0x534); +check_member(mt8186_mcucfg_regs, mp0_cpu7_nonwfx_ctrl, 0x538); +check_member(mt8186_mcucfg_regs, mp0_cpu7_nonwfx_cnt, 0x53c); +check_member(mt8186_mcucfg_regs, mp0_ses_apb_trig, 0x600); +check_member(mt8186_mcucfg_regs, wfx_ret_met_dbc_sel, 0x610); +check_member(mt8186_mcucfg_regs, adb_bist_cfg1, 0x620); +check_member(mt8186_mcucfg_regs, adb_bist_cfg2_md, 0x624); +check_member(mt8186_mcucfg_regs, adb_bist_cfg3_go, 0x628); +check_member(mt8186_mcucfg_regs, adb_bist_done, 0x62c); +check_member(mt8186_mcucfg_regs, adb_bist_pass, 0x630); +check_member(mt8186_mcucfg_regs, dfd_internal_ctl, 0x2040); +check_member(mt8186_mcucfg_regs, dfd_internal_counter, 0x2044); +check_member(mt8186_mcucfg_regs, dfd_internal_pwr_on, 0x2048); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_legth_0, 0x204c); +check_member(mt8186_mcucfg_regs, dfd_internal_shift_clk_ratio, 0x2050); +check_member(mt8186_mcucfg_regs, dfd_internal_counter_return, 0x2054); +check_member(mt8186_mcucfg_regs, dfd_internal_sram_access, 0x2058); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_1, 0x205c); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_2, 0x2060); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_3, 0x2064); +check_member(mt8186_mcucfg_regs, dfd_internal_test_so_0, 0x2068); +check_member(mt8186_mcucfg_regs, dfd_internal_test_so_1, 0x206c); +check_member(mt8186_mcucfg_regs, dfd_internal_num_of_test_so_gp, 0x2070); +check_member(mt8186_mcucfg_regs, dfd_internal_test_so_over_64, 0x2074); +check_member(mt8186_mcucfg_regs, dfd_internal_mask_out, 0x2078); +check_member(mt8186_mcucfg_regs, dfd_internal_sw_ns_trigger, 0x207c); +check_member(mt8186_mcucfg_regs, dfd_internal_mcsi, 0x2080); +check_member(mt8186_mcucfg_regs, dfd_internal_mcsi_sel_status, 0x2084); +check_member(mt8186_mcucfg_regs, dfd_v30_ctl, 0x2088); +check_member(mt8186_mcucfg_regs, dfd_v30_base_addr, 0x208c); +check_member(mt8186_mcucfg_regs, dfd_power_ctl, 0x2090); +check_member(mt8186_mcucfg_regs, dfd_reset_on, 0x2094); +check_member(mt8186_mcucfg_regs, dfd_test_si_0, 0x2098); +check_member(mt8186_mcucfg_regs, dfd_test_si_1, 0x209c); +check_member(mt8186_mcucfg_regs, dfd_status_clean, 0x20a0); +check_member(mt8186_mcucfg_regs, dfd_status_return, 0x20a4); +check_member(mt8186_mcucfg_regs, dfd_hw_trigger_mask, 0x20fc); +check_member(mt8186_mcucfg_regs, mcusys_par_wrap_dbg_mon_sel, 0x2200); +check_member(mt8186_mcucfg_regs, mcusys_par_wrap_dbg_mon, 0x2204); +check_member(mt8186_mcucfg_regs, mcusys_pinmux, 0x2208); +check_member(mt8186_mcucfg_regs, l3c_share_cfg0, 0x2210); +check_member(mt8186_mcucfg_regs, l3c_share_cfg1, 0x2214); +check_member(mt8186_mcucfg_regs, l3c_share_cfg2, 0x2218); +check_member(mt8186_mcucfg_regs, udi_cfg0, 0x2220); +check_member(mt8186_mcucfg_regs, udi_cfg1, 0x2224); +check_member(mt8186_mcucfg_regs, mcusys_core_status, 0x2230); +check_member(mt8186_mcucfg_regs, mcusys_base, 0x2260); +check_member(mt8186_mcucfg_regs, l3c_sram_base, 0x2264); +check_member(mt8186_mcucfg_regs, gic_periph_base, 0x2268); +check_member(mt8186_mcucfg_regs, cci_periph_base, 0x226c); +check_member(mt8186_mcucfg_regs, cci_periph_infra_base, 0x2270); +check_member(mt8186_mcucfg_regs, dfd_sram_base, 0x2274); +check_member(mt8186_mcucfg_regs, l3c_mm_sram_base, 0x2278); +check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0); +check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg1, 0x22a4); +check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg2, 0x22a8); +check_member(mt8186_mcucfg_regs, bus_plldiv_cfg, 0x22e0); +check_member(mt8186_mcucfg_regs, plldiv_ctl0, 0x22f0); +check_member(mt8186_mcucfg_regs, mcsi_ram_delsel0, 0x2300); +check_member(mt8186_mcucfg_regs, mcsi_ram_delsel1, 0x2304); +check_member(mt8186_mcucfg_regs, etb_ram_delsel0, 0x2320); +check_member(mt8186_mcucfg_regs, etb_cfg0, 0x2380); +check_member(mt8186_mcucfg_regs, cci_rgu, 0x2400); +check_member(mt8186_mcucfg_regs, mcsi_cfg0, 0x2410); +check_member(mt8186_mcucfg_regs, mcsi_cfg1, 0x2414); +check_member(mt8186_mcucfg_regs, mcsi_cfg2, 0x2418); +check_member(mt8186_mcucfg_regs, mcsi_cfg3, 0x241c); +check_member(mt8186_mcucfg_regs, mcsi_cfg4, 0x2420); +check_member(mt8186_mcucfg_regs, mcsic_dcm0, 0x2440); +check_member(mt8186_mcucfg_regs, mcsic_dcm1, 0x2444); +check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg0, 0x2500); +check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg2, 0x2508); +check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg4, 0x2510); +check_member(mt8186_mcucfg_regs, mp_misc_dcm_cfg0, 0x2518); +check_member(mt8186_mcucfg_regs, etb_ck_ctl, 0x2540); +check_member(mt8186_mcucfg_regs, dcc_cpu_con0, 0x2580); +check_member(mt8186_mcucfg_regs, dcc_cpu_con1, 0x2584); +check_member(mt8186_mcucfg_regs, dcc_cpu_con2, 0x2588); +check_member(mt8186_mcucfg_regs, dcc_bus_con0, 0x25a0); +check_member(mt8186_mcucfg_regs, mcusys_dcm_cfg0, 0x25c0); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en0, 0x2600); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en1, 0x2604); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en2, 0x2608); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en3, 0x260c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en4, 0x2610); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en5, 0x2614); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en6, 0x2618); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en7, 0x261c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en8, 0x2620); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en9, 0x2624); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en10, 0x2628); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en11, 0x262c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en12, 0x2630); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en13, 0x2634); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en14, 0x2638); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en15, 0x263c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en16, 0x2640); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en17, 0x2644); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en18, 0x2648); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en19, 0x264c); +check_member(mt8186_mcucfg_regs, int_pol_ctl0, 0x2650); +check_member(mt8186_mcucfg_regs, int_pol_ctl1, 0x2654); +check_member(mt8186_mcucfg_regs, int_pol_ctl2, 0x2658); +check_member(mt8186_mcucfg_regs, int_pol_ctl3, 0x265c); +check_member(mt8186_mcucfg_regs, int_pol_ctl4, 0x2660); +check_member(mt8186_mcucfg_regs, int_pol_ctl5, 0x2664); +check_member(mt8186_mcucfg_regs, int_pol_ctl6, 0x2668); +check_member(mt8186_mcucfg_regs, int_pol_ctl7, 0x266c); +check_member(mt8186_mcucfg_regs, int_pol_ctl8, 0x2670); +check_member(mt8186_mcucfg_regs, int_pol_ctl9, 0x2674); +check_member(mt8186_mcucfg_regs, int_pol_ctl10, 0x2678); +check_member(mt8186_mcucfg_regs, int_pol_ctl11, 0x267c); +check_member(mt8186_mcucfg_regs, int_pol_ctl12, 0x2680); +check_member(mt8186_mcucfg_regs, int_pol_ctl13, 0x2684); +check_member(mt8186_mcucfg_regs, int_pol_ctl14, 0x2688); +check_member(mt8186_mcucfg_regs, int_pol_ctl15, 0x268c); +check_member(mt8186_mcucfg_regs, int_pol_ctl16, 0x2690); +check_member(mt8186_mcucfg_regs, int_pol_ctl17, 0x2694); +check_member(mt8186_mcucfg_regs, int_pol_ctl18, 0x2698); +check_member(mt8186_mcucfg_regs, int_pol_ctl19, 0x269c); +check_member(mt8186_mcucfg_regs, int_msk_ctl0, 0x26a0); +check_member(mt8186_mcucfg_regs, int_msk_ctl1, 0x26a4); +check_member(mt8186_mcucfg_regs, int_msk_ctl2, 0x26a8); +check_member(mt8186_mcucfg_regs, int_msk_ctl3, 0x26ac); +check_member(mt8186_mcucfg_regs, int_msk_ctl4, 0x26b0); +check_member(mt8186_mcucfg_regs, int_msk_ctl5, 0x26b4); +check_member(mt8186_mcucfg_regs, int_msk_ctl6, 0x26b8); +check_member(mt8186_mcucfg_regs, int_msk_ctl7, 0x26bc); +check_member(mt8186_mcucfg_regs, int_msk_ctl8, 0x26c0); +check_member(mt8186_mcucfg_regs, int_msk_ctl9, 0x26c4); +check_member(mt8186_mcucfg_regs, int_msk_ctl10, 0x26c8); +check_member(mt8186_mcucfg_regs, int_msk_ctl11, 0x26cc); +check_member(mt8186_mcucfg_regs, int_msk_ctl12, 0x26d0); +check_member(mt8186_mcucfg_regs, int_msk_ctl13, 0x26d4); +check_member(mt8186_mcucfg_regs, int_msk_ctl14, 0x26d8); +check_member(mt8186_mcucfg_regs, int_msk_ctl15, 0x26dc); +check_member(mt8186_mcucfg_regs, int_msk_ctl16, 0x26e0); +check_member(mt8186_mcucfg_regs, int_msk_ctl17, 0x26e4); +check_member(mt8186_mcucfg_regs, int_msk_ctl18, 0x26e8); +check_member(mt8186_mcucfg_regs, int_msk_ctl19, 0x26ec); +check_member(mt8186_mcucfg_regs, int_msk_ctl_all, 0x26f4); +check_member(mt8186_mcucfg_regs, int_cfg_indirect_access, 0x26f8); +check_member(mt8186_mcucfg_regs, int_cfg_direct_access_en, 0x26fc); +check_member(mt8186_mcucfg_regs, fcm_spmc_sw_cfg1, 0x2700); +check_member(mt8186_mcucfg_regs, fcm_spmc_sw_cfg2, 0x2704); +check_member(mt8186_mcucfg_regs, fcm_spmc_wait_cfg, 0x2708); +check_member(mt8186_mcucfg_regs, fcm_spmc_sw_pchannel, 0x270c); +check_member(mt8186_mcucfg_regs, fcm_spmc_pwr_status, 0x2710); +check_member(mt8186_mcucfg_regs, fcm_spmc_off_thres, 0x2714); +check_member(mt8186_mcucfg_regs, fcm_spmc_wdt_latch_info, 0x2718); +check_member(mt8186_mcucfg_regs, mcusys_spmc_sw_cfg, 0x2740); +check_member(mt8186_mcucfg_regs, mcusys_spmc_wait_cfg, 0x2744); +check_member(mt8186_mcucfg_regs, mcusys_spmc_pwr_status, 0x2748); +check_member(mt8186_mcucfg_regs, cpc_pllbuck_req_ctrl, 0x2800); +check_member(mt8186_mcucfg_regs, mcusys_pwr_ctrl, 0x2804); +check_member(mt8186_mcucfg_regs, cpusys_pwr_ctrl, 0x2808); +check_member(mt8186_mcucfg_regs, sw_gic_wakeup_req, 0x280c); +check_member(mt8186_mcucfg_regs, cpc_pllbuck_arb_weight, 0x2810); +check_member(mt8186_mcucfg_regs, cpc_flow_ctrl_cfg, 0x2814); +check_member(mt8186_mcucfg_regs, cpc_last_core_req, 0x2818); +check_member(mt8186_mcucfg_regs, cpc_cpusys_last_core_resp, 0x281c); +check_member(mt8186_mcucfg_regs, cpc_mcusys_last_core_resp, 0x2824); +check_member(mt8186_mcucfg_regs, cpc_pwr_on_mask, 0x2828); +check_member(mt8186_mcucfg_regs, cpc_spmc_pwr_status, 0x2840); +check_member(mt8186_mcucfg_regs, cpc_core_cur_fsm, 0x2844); +check_member(mt8186_mcucfg_regs, cpc_cpusys_mcusys_cur_fsm, 0x2848); +check_member(mt8186_mcucfg_regs, cpc_wakeup_req, 0x284c); +check_member(mt8186_mcucfg_regs, cpc_turbo_ctrl, 0x285c); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_ctrl, 0x2860); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_ctrl, 0x2864); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_ctrl, 0x2868); +check_member(mt8186_mcucfg_regs, cpc_turbo_pwr_on_mask, 0x286c); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_req, 0x2870); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_req, 0x2874); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_req, 0x2878); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_resp, 0x2880); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_resp, 0x2884); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_resp, 0x2888); +check_member(mt8186_mcucfg_regs, cpc_coh_block_thres, 0x288c); +check_member(mt8186_mcucfg_regs, cpc_int_status, 0x2890); +check_member(mt8186_mcucfg_regs, cpc_int_enable, 0x2894); +check_member(mt8186_mcucfg_regs, pllbuck_group_func, 0x2898); +check_member(mt8186_mcucfg_regs, cpc_dcm_enable, 0x289c); +check_member(mt8186_mcucfg_regs, cpc_pllbuck_state, 0x28a0); +check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint, 0x28a4); +check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint_set, 0x28a8); +check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint_clear, 0x28ac); +check_member(mt8186_mcucfg_regs, emi_wfifo, 0x2900); +check_member(mt8186_mcucfg_regs, axi1to4_cfg, 0x2904); +check_member(mt8186_mcucfg_regs, emi_adb_edge_sel, 0x290c); +check_member(mt8186_mcucfg_regs, sclk_cfg_slow_down_ck, 0x2920); +check_member(mt8186_mcucfg_regs, mcusys_dbg_mon_sel, 0x2990); +check_member(mt8186_mcucfg_regs, mcusys_dbg_mon, 0x2994); +check_member(mt8186_mcucfg_regs, gic_acao_ctl0, 0x2a80); +check_member(mt8186_mcucfg_regs, gic_acao_ctl1, 0x2a84); +check_member(mt8186_mcucfg_regs, gic_acao_ctl2, 0x2a88); +check_member(mt8186_mcucfg_regs, spmc_dbg_setting, 0x2b00); +check_member(mt8186_mcucfg_regs, kernel_base_l, 0x2b04); +check_member(mt8186_mcucfg_regs, kernel_base_h, 0x2b08); +check_member(mt8186_mcucfg_regs, systime_base_l, 0x2b0c); +check_member(mt8186_mcucfg_regs, systime_base_h, 0x2b10); +check_member(mt8186_mcucfg_regs, trace_data_selection, 0x2b14); +check_member(mt8186_mcucfg_regs, trace_data_entry0_l, 0x2b20); +check_member(mt8186_mcucfg_regs, trace_data_entry0_h, 0x2b24); +check_member(mt8186_mcucfg_regs, trace_data_entry1_l, 0x2b28); +check_member(mt8186_mcucfg_regs, trace_data_entry1_h, 0x2b2c); +check_member(mt8186_mcucfg_regs, trace_data_entry2_l, 0x2b30); +check_member(mt8186_mcucfg_regs, trace_data_entry2_h, 0x2b34); +check_member(mt8186_mcucfg_regs, trace_data_entry3_l, 0x2b38); +check_member(mt8186_mcucfg_regs, trace_data_entry3_h, 0x2b3c); +check_member(mt8186_mcucfg_regs, cpu0_on_off_latency, 0x2b40); +check_member(mt8186_mcucfg_regs, cpu1_on_off_latency, 0x2b44); +check_member(mt8186_mcucfg_regs, cpu2_on_off_latency, 0x2b48); +check_member(mt8186_mcucfg_regs, cpu3_on_off_latency, 0x2b4c); +check_member(mt8186_mcucfg_regs, cpu4_on_off_latency, 0x2b50); +check_member(mt8186_mcucfg_regs, cpu5_on_off_latency, 0x2b54); +check_member(mt8186_mcucfg_regs, cpu6_on_off_latency, 0x2b58); +check_member(mt8186_mcucfg_regs, cpu7_on_off_latency, 0x2b5c); +check_member(mt8186_mcucfg_regs, cluster_off_latency, 0x2b60); +check_member(mt8186_mcucfg_regs, cluster_on_latency, 0x2b64); +check_member(mt8186_mcucfg_regs, mcusys_on_off_latency, 0x2b68); +check_member(mt8186_mcucfg_regs, cluster_off_dormant_counter, 0x2b70); +check_member(mt8186_mcucfg_regs, cluster_off_dormant_counter_clear, 0x2b74); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info1, 0x2b80); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info2, 0x2b84); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info3, 0x2b88); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info4, 0x2b8c); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info5, 0x2b90); +check_member(mt8186_mcucfg_regs, cpc_pmu_ctrl, 0x2b94); +check_member(mt8186_mcucfg_regs, cpc_pmu_cnt_clr, 0x2b98); +check_member(mt8186_mcucfg_regs, cpc_pmu_cnt0, 0x2b9c); +check_member(mt8186_mcucfg_regs, ildo_vproc2_en, 0x2d00); +check_member(mt8186_mcucfg_regs, pikachu_event, 0x2e00); +check_member(mt8186_mcucfg_regs, pikachu_status, 0x2e04); +check_member(mt8186_mcucfg_regs, cpu0_drcc_ao_config, 0x3000); +check_member(mt8186_mcucfg_regs, cpu0_resereved_reg, 0x31f8); +check_member(mt8186_mcucfg_regs, cpu0_resereved_reg_rd, 0x31fc); +check_member(mt8186_mcucfg_regs, cpu1_drcc_ao_config, 0x3200); +check_member(mt8186_mcucfg_regs, cpu1_resereved_reg, 0x33f8); +check_member(mt8186_mcucfg_regs, cpu1_resereved_reg_rd, 0x33fc); +check_member(mt8186_mcucfg_regs, cpu2_drcc_ao_config, 0x3400); +check_member(mt8186_mcucfg_regs, cpu2_resereved_reg, 0x35f8); +check_member(mt8186_mcucfg_regs, cpu2_resereved_reg_rd, 0x35fc); +check_member(mt8186_mcucfg_regs, cpu3_drcc_ao_config, 0x3600); +check_member(mt8186_mcucfg_regs, cpu3_resereved_reg, 0x37f8); +check_member(mt8186_mcucfg_regs, cpu3_resereved_reg_rd, 0x37fc); +check_member(mt8186_mcucfg_regs, cpu4_drcc_ao_config, 0x3800); +check_member(mt8186_mcucfg_regs, cpu4_resereved_reg, 0x39f8); +check_member(mt8186_mcucfg_regs, cpu4_resereved_reg_rd, 0x39fc); +check_member(mt8186_mcucfg_regs, cpu5_drcc_ao_config, 0x3a00); +check_member(mt8186_mcucfg_regs, cpu5_resereved_reg, 0x3bf8); +check_member(mt8186_mcucfg_regs, cpu5_resereved_reg_rd, 0x3bfc); +check_member(mt8186_mcucfg_regs, cpu6_drcc_ao_config, 0x3c00); +check_member(mt8186_mcucfg_regs, cpu6_resereved_reg, 0x3df8); +check_member(mt8186_mcucfg_regs, cpu6_resereved_reg_rd, 0x3dfc); +check_member(mt8186_mcucfg_regs, cpu7_drcc_ao_config, 0x3e00); +check_member(mt8186_mcucfg_regs, cpu7_resereved_reg, 0x3ff8); +check_member(mt8186_mcucfg_regs, cpu7_resereved_reg_rd, 0x3ffc); +check_member(mt8186_mcucfg_regs, mp0_l3_data_ram_delsel, 0x4840); +check_member(mt8186_mcucfg_regs, mp0_l3_tag_ram_delsel, 0x4844); +check_member(mt8186_mcucfg_regs, mp0_l3_victim_ram_delsel, 0x4848); +check_member(mt8186_mcucfg_regs, mp0_l3_scu_sf_ram_delsel, 0x484c); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg0, 0x4880); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg1, 0x4884); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg2, 0x4888); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg3, 0x488c); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg4, 0x4890); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg5, 0x4894); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg6, 0x4898); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg7, 0x489c); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg8, 0x48a0); +check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity1, 0x48c0); +check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity2, 0x48c4); +check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity3, 0x48c8); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg0, 0x48d0); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg4, 0x48e0); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg5, 0x48e4); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg6, 0x48e8); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg7, 0x48ec); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg8, 0x4900); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg9, 0x4904); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg10, 0x4908); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg11, 0x490c); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg12, 0x4910); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg13, 0x4914); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg14, 0x4918); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg15, 0x491c); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg16, 0x4920); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg17, 0x4924); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg18, 0x4928); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg19, 0x492c); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg20, 0x4930); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg21, 0x4934); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg22, 0x4938); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg23, 0x493c); +check_member(mt8186_mcucfg_regs, mp0_victim_rd_mask, 0x4944); +check_member(mt8186_mcucfg_regs, cpu_type0_spmc0_cfg, 0x4c00); +check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel0_cfg, 0x4c20); +check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel1_cfg, 0x4c24); +check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel2_cfg, 0x4c28); +check_member(mt8186_mcucfg_regs, cpu_type1_spmc0_cfg, 0x4d00); +check_member(mt8186_mcucfg_regs, cpu_type1_mpmmen, 0x4d10); +check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel0_cfg, 0x4d20); +check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel1_cfg, 0x4d24); +check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel2_cfg, 0x4d28); +check_member(mt8186_mcucfg_regs, plldiv_turbo, 0x4e00); +check_member(mt8186_mcucfg_regs, plldiv_percore_dfs_1, 0x4e04); +check_member(mt8186_mcucfg_regs, plldiv_percore_dfs_2, 0x4e08); +check_member(mt8186_mcucfg_regs, plldiv_imax_cg, 0x4e0c); +check_member(mt8186_mcucfg_regs, plldiv_imax_int, 0x4e10); +check_member(mt8186_mcucfg_regs, plldiv_imax_detector, 0x4e14); +check_member(mt8186_mcucfg_regs, plldiv_little_reserved, 0x4e18); +check_member(mt8186_mcucfg_regs, plldiv_big_reserved, 0x4e1c); +check_member(mt8186_mcucfg_regs, plldiv_bus_reserved, 0x4e20); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg1, 0x7fe4); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2, 0x7fe8); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3, 0x7fec); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg0_rd, 0x7ff0); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg1_rd, 0x7ff4); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2_rd, 0x7ff8); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); + +static struct mt8186_mcucfg_regs *const mt8186_mcucfg = (void *)MCUCFG_BASE; + +#endif /* SOC_MEDIATEK_MT8186_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h index 0634a3b72e0d..4638f50a9259 100644 --- a/src/soc/mediatek/mt8186/include/soc/pll.h +++ b/src/soc/mediatek/mt8186/include/soc/pll.h @@ -8,16 +8,503 @@ #ifndef SOC_MEDIATEK_MT8186_PLL_H #define SOC_MEDIATEK_MT8186_PLL_H +#include <device/mmio.h> +#include <types.h> #include <soc/pll_common.h> +struct mtk_topckgen_regs { + u32 clk_mode; + u32 clk_cfg_update; + u32 clk_cfg_update1; + u32 reserved1[13]; + u32 clk_cfg_0; + u32 clk_cfg_0_set; + u32 clk_cfg_0_clr; + u32 reserved2[1]; + u32 clk_cfg_1; + u32 clk_cfg_1_set; + u32 clk_cfg_1_clr; + u32 reserved3[1]; + u32 clk_cfg_2; + u32 clk_cfg_2_set; + u32 clk_cfg_2_clr; + u32 reserved4[1]; + u32 clk_cfg_3; + u32 clk_cfg_3_set; + u32 clk_cfg_3_clr; + u32 reserved5[1]; + u32 clk_cfg_4; + u32 clk_cfg_4_set; + u32 clk_cfg_4_clr; + u32 reserved6[1]; + u32 clk_cfg_5; + u32 clk_cfg_5_set; + u32 clk_cfg_5_clr; + u32 reserved7[1]; + u32 clk_cfg_6; + u32 clk_cfg_6_set; + u32 clk_cfg_6_clr; + u32 reserved8[1]; + u32 clk_cfg_7; + u32 clk_cfg_7_set; + u32 clk_cfg_7_clr; + u32 reserved9[1]; + u32 clk_cfg_8; + u32 clk_cfg_8_set; + u32 clk_cfg_8_clr; + u32 reserved10[1]; + u32 clk_cfg_9; + u32 clk_cfg_9_set; + u32 clk_cfg_9_clr; + u32 reserved11[1]; + u32 clk_cfg_10; + u32 clk_cfg_10_set; + u32 clk_cfg_10_clr; + u32 clk_cfg_11; + u32 clk_cfg_11_set; + u32 clk_cfg_11_clr; + u32 reserved12[2]; + u32 clk_cfg_12; + u32 clk_cfg_12_set; + u32 clk_cfg_12_clr; + u32 reserved13[1]; + u32 clk_cfg_13; + u32 clk_cfg_13_set; + u32 clk_cfg_13_clr; + u32 reserved14[1]; + u32 clk_cfg_14; + u32 clk_cfg_14_set; + u32 clk_cfg_14_clr; + u32 reserved15[1]; + u32 clk_cfg_20; + u32 clk_cfg_20_set; + u32 clk_cfg_20_clr; + u32 reserved16[1]; + u32 clk_misc_cfg_0; + u32 reserved17[3]; + u32 clk_misc_cfg_1; + u32 reserved18[10]; + u32 clk_dbg_cfg; + u32 clk_cfg_15; + u32 clk_cfg_15_set; + u32 clk_cfg_15_clr; + u32 reserved19[29]; + u32 clk_scp_cfg_0; + u32 reserved20[3]; + u32 clk_scp_cfg_1; + u32 reserved21[3]; + u32 clk26cali_0; + u32 clk26cali_1; + u32 reserved22[2]; + u32 cksta_reg; + u32 cksta_reg1; + u32 reserved23[50]; + u32 clkmon_clk_sel_reg; + u32 clkmon_k1_reg; + u32 reserved24[6]; + u32 clk_auddiv_0; + u32 clk_auddiv_1; + u32 clk_auddiv_2; + u32 aud_top_cfg; + u32 aud_top_mon; + u32 clk_auddiv_3; + u32 reserved25[1]; + u32 usb_top_cfg; + u32 reserved26[112]; + u32 clk_extck_reg; +}; + +check_member(mtk_topckgen_regs, clk_mode, 0x0); +check_member(mtk_topckgen_regs, clk_cfg_update, 0x4); +check_member(mtk_topckgen_regs, clk_cfg_update1, 0x8); +check_member(mtk_topckgen_regs, clk_cfg_0, 0x40); +check_member(mtk_topckgen_regs, clk_cfg_0_set, 0x44); +check_member(mtk_topckgen_regs, clk_cfg_0_clr, 0x48); +check_member(mtk_topckgen_regs, clk_cfg_1, 0x50); +check_member(mtk_topckgen_regs, clk_cfg_1_set, 0x54); +check_member(mtk_topckgen_regs, clk_cfg_1_clr, 0x58); +check_member(mtk_topckgen_regs, clk_cfg_2, 0x60); +check_member(mtk_topckgen_regs, clk_cfg_2_set, 0x64); +check_member(mtk_topckgen_regs, clk_cfg_2_clr, 0x68); +check_member(mtk_topckgen_regs, clk_cfg_3, 0x70); +check_member(mtk_topckgen_regs, clk_cfg_3_set, 0x74); +check_member(mtk_topckgen_regs, clk_cfg_3_clr, 0x78); +check_member(mtk_topckgen_regs, clk_cfg_4, 0x80); +check_member(mtk_topckgen_regs, clk_cfg_4_set, 0x84); +check_member(mtk_topckgen_regs, clk_cfg_4_clr, 0x88); +check_member(mtk_topckgen_regs, clk_cfg_5, 0x90); +check_member(mtk_topckgen_regs, clk_cfg_5_set, 0x94); +check_member(mtk_topckgen_regs, clk_cfg_5_clr, 0x98); +check_member(mtk_topckgen_regs, clk_cfg_6, 0xa0); +check_member(mtk_topckgen_regs, clk_cfg_6_set, 0xa4); +check_member(mtk_topckgen_regs, clk_cfg_6_clr, 0xa8); +check_member(mtk_topckgen_regs, clk_cfg_7, 0xb0); +check_member(mtk_topckgen_regs, clk_cfg_7_set, 0xb4); +check_member(mtk_topckgen_regs, clk_cfg_7_clr, 0xb8); +check_member(mtk_topckgen_regs, clk_cfg_8, 0xc0); +check_member(mtk_topckgen_regs, clk_cfg_8_set, 0xc4); +check_member(mtk_topckgen_regs, clk_cfg_8_clr, 0xc8); +check_member(mtk_topckgen_regs, clk_cfg_9, 0xd0); +check_member(mtk_topckgen_regs, clk_cfg_9_set, 0xd4); +check_member(mtk_topckgen_regs, clk_cfg_9_clr, 0xd8); +check_member(mtk_topckgen_regs, clk_cfg_10, 0xe0); +check_member(mtk_topckgen_regs, clk_cfg_10_set, 0xe4); +check_member(mtk_topckgen_regs, clk_cfg_10_clr, 0xe8); +check_member(mtk_topckgen_regs, clk_cfg_11, 0xec); +check_member(mtk_topckgen_regs, clk_cfg_11_set, 0xf0); +check_member(mtk_topckgen_regs, clk_cfg_11_clr, 0xf4); +check_member(mtk_topckgen_regs, clk_cfg_12, 0x100); +check_member(mtk_topckgen_regs, clk_cfg_12_set, 0x104); +check_member(mtk_topckgen_regs, clk_cfg_12_clr, 0x108); +check_member(mtk_topckgen_regs, clk_cfg_13, 0x110); +check_member(mtk_topckgen_regs, clk_cfg_13_set, 0x114); +check_member(mtk_topckgen_regs, clk_cfg_13_clr, 0x118); +check_member(mtk_topckgen_regs, clk_cfg_14, 0x120); +check_member(mtk_topckgen_regs, clk_cfg_14_set, 0x124); +check_member(mtk_topckgen_regs, clk_cfg_14_clr, 0x128); +check_member(mtk_topckgen_regs, clk_cfg_20, 0x130); +check_member(mtk_topckgen_regs, clk_cfg_20_set, 0x134); +check_member(mtk_topckgen_regs, clk_cfg_20_clr, 0x138); +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x140); +check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x150); +check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x17c); +check_member(mtk_topckgen_regs, clk_cfg_15, 0x180); +check_member(mtk_topckgen_regs, clk_cfg_15_set, 0x184); +check_member(mtk_topckgen_regs, clk_cfg_15_clr, 0x188); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x200); +check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x210); +check_member(mtk_topckgen_regs, clk26cali_0, 0x220); +check_member(mtk_topckgen_regs, clk26cali_1, 0x224); +check_member(mtk_topckgen_regs, cksta_reg, 0x230); +check_member(mtk_topckgen_regs, cksta_reg1, 0x234); +check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x300); +check_member(mtk_topckgen_regs, clkmon_k1_reg, 0x304); +check_member(mtk_topckgen_regs, clk_auddiv_0, 0x320); +check_member(mtk_topckgen_regs, clk_auddiv_1, 0x324); +check_member(mtk_topckgen_regs, clk_auddiv_2, 0x328); +check_member(mtk_topckgen_regs, aud_top_cfg, 0x32c); +check_member(mtk_topckgen_regs, aud_top_mon, 0x330); +check_member(mtk_topckgen_regs, clk_auddiv_3, 0x334); +check_member(mtk_topckgen_regs, usb_top_cfg, 0x33c); +check_member(mtk_topckgen_regs, clk_extck_reg, 0x500); + +struct mtk_apmixed_regs { + u32 ap_pll_con0; + u32 ap_pll_con1; + u32 ap_pll_con2; + u32 ap_pll_con3; + u32 ap_pll_con4; + u32 ap_pll_con5; + u32 clksq_stb_con0; + u32 pll_pwr_con0; + u32 pll_pwr_con1; + u32 pll_iso_con0; + u32 pll_iso_con1; + u32 pll_stb_con0; + u32 div_stb_con0; + u32 pll_chg_con0; + u32 pll_test_con0; + u32 pll_test_con1; + u32 apll1_tuner_con0; + u32 apll2_tuner_con0; + u32 reserved1[2]; + u32 pllon_con0; + u32 pllon_con1; + u32 reserved2[106]; + u32 ap_pllgp1_con0; + u32 armpll_ll_con0; + u32 armpll_ll_con1; + u32 armpll_ll_con2; + u32 armpll_ll_con3; + u32 armpll_bl_con0; + u32 armpll_bl_con1; + u32 armpll_bl_con2; + u32 armpll_bl_con3; + u32 ccipll_con0; + u32 ccipll_con1; + u32 ccipll_con2; + u32 ccipll_con3; + u32 apupll_con0; + u32 apupll_con1; + u32 apupll_con2; + u32 apupll_con3; + u32 mainpll_con0; + u32 mainpll_con1; + u32 mainpll_con2; + u32 mainpll_con3; + u32 mmpll_con0; + u32 mmpll_con1; + u32 mmpll_con2; + u32 mmpll_con3; + u32 tvdpll_con0; + u32 tvdpll_con1; + u32 tvdpll_con2; + u32 tvdpll_con3; + u32 mpll_con0; + u32 mpll_con1; + u32 mpll_con2; + u32 mpll_con3; + u32 reserved3[31]; + u32 ap_pllgp2_con0; + u32 adsppll_con0; + u32 adsppll_con1; + u32 adsppll_con2; + u32 adsppll_con3; + u32 mfgpll_con0; + u32 mfgpll_con1; + u32 mfgpll_con2; + u32 mfgpll_con3; + u32 univpll_con0; + u32 univpll_con1; + u32 univpll_con2; + u32 univpll_con3; + u32 apll1_con0; + u32 apll1_con1; + u32 apll1_con2; + u32 apll1_con3; + u32 apll1_con4; + u32 apll2_con0; + u32 apll2_con1; + u32 apll2_con2; + u32 apll2_con3; + u32 apll2_con4; + u32 nnapll_con0; + u32 nnapll_con1; + u32 nnapll_con2; + u32 nnapll_con3; + u32 nna2pll_con0; + u32 nna2pll_con1; + u32 nna2pll_con2; + u32 nna2pll_con3; + u32 mdbrppll_con0; + u32 mdbrppll_con1; + u32 mdbrppll_con2; + u32 mdbrppll_con3; + u32 msdcpll_con0; + u32 msdcpll_con1; + u32 msdcpll_con2; + u32 msdcpll_con3; + u32 mdbpipll_con0; + u32 mdbpipll_con1; + u32 mdbpipll_con2; + u32 mdbpipll_con3; + u32 reserved4[21]; + u32 ap_auxadc_con0; + u32 ap_auxadc_con1; + u32 reserved5[30]; + u32 ap_tsense_con0; + u32 ap_tsense_con1; + u32 ap_tsense_con2; + u32 reserved6[29]; + u32 ulposc_con0; + u32 ulposc_con1; + u32 reserved7[30]; + u32 ulposc2_con0; + u32 ulposc2_con1; + u32 reserved8[158]; + u32 ap_abist_mon_con0; + u32 ap_abist_mon_con1; + u32 ap_abist_mon_con2; + u32 ap_abist_mon_con3; + u32 occscan_con0; + u32 clkdiv_con0; + u32 occscan_con1; + u32 occscan_con2; + u32 occscan_con3; + u32 mcu_occscan_con0; + u32 occscan_con4; + u32 occscan_con5; + u32 reserved9[52]; + u32 rsv_rw0_con0; + u32 rsv_rw1_con0; + u32 rsv_ro_con0; +}; +check_member(mtk_apmixed_regs, ap_pll_con0, 0x0); +check_member(mtk_apmixed_regs, ap_pll_con1, 0x4); +check_member(mtk_apmixed_regs, ap_pll_con2, 0x8); +check_member(mtk_apmixed_regs, ap_pll_con3, 0xc); +check_member(mtk_apmixed_regs, ap_pll_con4, 0x10); +check_member(mtk_apmixed_regs, ap_pll_con5, 0x14); +check_member(mtk_apmixed_regs, clksq_stb_con0, 0x18); +check_member(mtk_apmixed_regs, pll_pwr_con0, 0x1c); +check_member(mtk_apmixed_regs, pll_pwr_con1, 0x20); +check_member(mtk_apmixed_regs, pll_iso_con0, 0x24); +check_member(mtk_apmixed_regs, pll_iso_con1, 0x28); +check_member(mtk_apmixed_regs, pll_stb_con0, 0x2c); +check_member(mtk_apmixed_regs, div_stb_con0, 0x30); +check_member(mtk_apmixed_regs, pll_chg_con0, 0x34); +check_member(mtk_apmixed_regs, pll_test_con0, 0x38); +check_member(mtk_apmixed_regs, pll_test_con1, 0x3c); +check_member(mtk_apmixed_regs, apll1_tuner_con0, 0x40); +check_member(mtk_apmixed_regs, apll2_tuner_con0, 0x44); +check_member(mtk_apmixed_regs, pllon_con0, 0x50); +check_member(mtk_apmixed_regs, pllon_con1, 0x54); +check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x200); +check_member(mtk_apmixed_regs, armpll_ll_con0, 0x204); +check_member(mtk_apmixed_regs, armpll_ll_con1, 0x208); +check_member(mtk_apmixed_regs, armpll_ll_con2, 0x20c); +check_member(mtk_apmixed_regs, armpll_ll_con3, 0x210); +check_member(mtk_apmixed_regs, armpll_bl_con0, 0x214); +check_member(mtk_apmixed_regs, armpll_bl_con1, 0x218); +check_member(mtk_apmixed_regs, armpll_bl_con2, 0x21c); +check_member(mtk_apmixed_regs, armpll_bl_con3, 0x220); +check_member(mtk_apmixed_regs, ccipll_con0, 0x224); +check_member(mtk_apmixed_regs, ccipll_con1, 0x228); +check_member(mtk_apmixed_regs, ccipll_con2, 0x22c); +check_member(mtk_apmixed_regs, ccipll_con3, 0x230); +check_member(mtk_apmixed_regs, apupll_con0, 0x234); +check_member(mtk_apmixed_regs, apupll_con1, 0x238); +check_member(mtk_apmixed_regs, apupll_con2, 0x23c); +check_member(mtk_apmixed_regs, apupll_con3, 0x240); +check_member(mtk_apmixed_regs, mainpll_con0, 0x244); +check_member(mtk_apmixed_regs, mainpll_con1, 0x248); +check_member(mtk_apmixed_regs, mainpll_con2, 0x24c); +check_member(mtk_apmixed_regs, mainpll_con3, 0x250); +check_member(mtk_apmixed_regs, mmpll_con0, 0x254); +check_member(mtk_apmixed_regs, mmpll_con1, 0x258); +check_member(mtk_apmixed_regs, mmpll_con2, 0x25c); +check_member(mtk_apmixed_regs, mmpll_con3, 0x260); +check_member(mtk_apmixed_regs, tvdpll_con0, 0x264); +check_member(mtk_apmixed_regs, tvdpll_con1, 0x268); +check_member(mtk_apmixed_regs, tvdpll_con2, 0x26c); +check_member(mtk_apmixed_regs, tvdpll_con3, 0x270); +check_member(mtk_apmixed_regs, mpll_con0, 0x274); +check_member(mtk_apmixed_regs, mpll_con1, 0x278); +check_member(mtk_apmixed_regs, mpll_con2, 0x27c); +check_member(mtk_apmixed_regs, mpll_con3, 0x280); +check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x300); +check_member(mtk_apmixed_regs, adsppll_con0, 0x304); +check_member(mtk_apmixed_regs, adsppll_con1, 0x308); +check_member(mtk_apmixed_regs, adsppll_con2, 0x30c); +check_member(mtk_apmixed_regs, adsppll_con3, 0x310); +check_member(mtk_apmixed_regs, mfgpll_con0, 0x314); +check_member(mtk_apmixed_regs, mfgpll_con1, 0x318); +check_member(mtk_apmixed_regs, mfgpll_con2, 0x31c); +check_member(mtk_apmixed_regs, mfgpll_con3, 0x320); +check_member(mtk_apmixed_regs, univpll_con0, 0x324); +check_member(mtk_apmixed_regs, univpll_con1, 0x328); +check_member(mtk_apmixed_regs, univpll_con2, 0x32c); +check_member(mtk_apmixed_regs, univpll_con3, 0x330); +check_member(mtk_apmixed_regs, apll1_con0, 0x334); +check_member(mtk_apmixed_regs, apll1_con1, 0x338); +check_member(mtk_apmixed_regs, apll1_con2, 0x33c); +check_member(mtk_apmixed_regs, apll1_con3, 0x340); +check_member(mtk_apmixed_regs, apll1_con4, 0x344); +check_member(mtk_apmixed_regs, apll2_con0, 0x348); +check_member(mtk_apmixed_regs, apll2_con1, 0x34c); +check_member(mtk_apmixed_regs, apll2_con2, 0x350); +check_member(mtk_apmixed_regs, apll2_con3, 0x354); +check_member(mtk_apmixed_regs, apll2_con4, 0x358); +check_member(mtk_apmixed_regs, nnapll_con0, 0x35c); +check_member(mtk_apmixed_regs, nnapll_con1, 0x360); +check_member(mtk_apmixed_regs, nnapll_con2, 0x364); +check_member(mtk_apmixed_regs, nnapll_con3, 0x368); +check_member(mtk_apmixed_regs, nna2pll_con0, 0x36c); +check_member(mtk_apmixed_regs, nna2pll_con1, 0x370); +check_member(mtk_apmixed_regs, nna2pll_con2, 0x374); +check_member(mtk_apmixed_regs, nna2pll_con3, 0x378); +check_member(mtk_apmixed_regs, mdbrppll_con0, 0x37c); +check_member(mtk_apmixed_regs, mdbrppll_con1, 0x380); +check_member(mtk_apmixed_regs, mdbrppll_con2, 0x384); +check_member(mtk_apmixed_regs, mdbrppll_con3, 0x388); +check_member(mtk_apmixed_regs, msdcpll_con0, 0x38c); +check_member(mtk_apmixed_regs, msdcpll_con1, 0x390); +check_member(mtk_apmixed_regs, msdcpll_con2, 0x394); +check_member(mtk_apmixed_regs, msdcpll_con3, 0x398); +check_member(mtk_apmixed_regs, mdbpipll_con0, 0x39c); +check_member(mtk_apmixed_regs, mdbpipll_con1, 0x3a0); +check_member(mtk_apmixed_regs, mdbpipll_con2, 0x3a4); +check_member(mtk_apmixed_regs, mdbpipll_con3, 0x3a8); +check_member(mtk_apmixed_regs, ap_auxadc_con0, 0x400); +check_member(mtk_apmixed_regs, ap_auxadc_con1, 0x404); +check_member(mtk_apmixed_regs, ap_tsense_con0, 0x480); +check_member(mtk_apmixed_regs, ap_tsense_con1, 0x484); +check_member(mtk_apmixed_regs, ap_tsense_con2, 0x488); +check_member(mtk_apmixed_regs, ulposc_con0, 0x500); +check_member(mtk_apmixed_regs, ulposc_con1, 0x504); +check_member(mtk_apmixed_regs, ulposc2_con0, 0x580); +check_member(mtk_apmixed_regs, ulposc2_con1, 0x584); +check_member(mtk_apmixed_regs, ap_abist_mon_con0, 0x800); +check_member(mtk_apmixed_regs, ap_abist_mon_con1, 0x804); +check_member(mtk_apmixed_regs, ap_abist_mon_con2, 0x808); +check_member(mtk_apmixed_regs, ap_abist_mon_con3, 0x80c); +check_member(mtk_apmixed_regs, occscan_con0, 0x810); +check_member(mtk_apmixed_regs, clkdiv_con0, 0x814); +check_member(mtk_apmixed_regs, occscan_con1, 0x818); +check_member(mtk_apmixed_regs, occscan_con2, 0x81c); +check_member(mtk_apmixed_regs, occscan_con3, 0x820); +check_member(mtk_apmixed_regs, mcu_occscan_con0, 0x824); +check_member(mtk_apmixed_regs, occscan_con4, 0x828); +check_member(mtk_apmixed_regs, occscan_con5, 0x82c); +check_member(mtk_apmixed_regs, rsv_rw0_con0, 0x900); +check_member(mtk_apmixed_regs, rsv_rw1_con0, 0x904); +check_member(mtk_apmixed_regs, rsv_ro_con0, 0x908); + +enum { + PLL_CKSQ_ON_DELAY = 100, + PLL_PWR_ON_DELAY = 30, + PLL_ISO_DELAY = 1, + PLL_EN_DELAY = 20, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +enum { + MT8186_PLL_EN = 0x1 << 0, + GLITCH_FREE_EN = 0x1 << 4, + PLL_DIV_EN = 0xff << 24, +}; + +enum { + ARMPLL_DIVIDER_PLL1_EN = 0x1 << 4, + ARMPLL_DIVIDER_PLL2_EN = 0x1 << 5, +}; + +enum { + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_26M = 0x0 << 9, +}; + +/* PLL rate */ +enum { + ARMPLL_LL_HZ = 1280 * MHz, + ARMPLL_BL_HZ = 1085 * MHz, + CCIPLL_HZ = 800 * MHz, + MAINPLL_HZ = 1092 * MHz, + UNIV2PLL_HZ = 2496UL * MHz, + MSDCPLL_HZ = 384 * MHz, + MMPLL_HZ = 560 * MHz, + NNAPLL_HZ = 800 * MHz, + NNA2PLL_HZ = 800 * MHz, + ADSPPLL_HZ = 800 * MHz, + MFGPLL_HZ = 250 * MHz, + TVDPLL_HZ = 297 * MHz, + APLL1_HZ = 180633600, + APLL2_HZ = 196608 * KHz, +}; + /* top_div rate */ enum { CLK26M_HZ = 26 * MHz, + UNIVPLL_D6_D2_HZ = UNIV2PLL_HZ / 2 / 6 / 2, }; /* top_mux rate */ enum { + SPI_HZ = UNIVPLL_D6_D2_HZ, UART_HZ = CLK26M_HZ, }; +DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_0_ENABLE, 12, 12) +DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) #endif /* SOC_MEDIATEK_MT8186_PLL_H */ diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c new file mode 100644 index 000000000000..8201a5afff19 --- /dev/null +++ b/src/soc/mediatek/mt8186/pll.c @@ -0,0 +1,543 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.2 + */ + +#include <console/console.h> +#include <device/mmio.h> +#include <delay.h> +#include <stddef.h> +#include <timer.h> + +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/mcucfg.h> +#include <soc/pll.h> + +enum mux_id { + TOP_AXI_SEL, + TOP_SCP_SEL, + TOP_MFG_SEL, + TOP_CAMTG_SEL, + TOP_CAMTG1_SEL, + TOP_CAMTG2_SEL, + TOP_CAMTG3_SEL, + TOP_CAMTG4_SEL, + TOP_CAMTG5_SEL, + TOP_CAMTG6_SEL, + TOP_UART_SEL, + TOP_SPI_SEL, + TOP_MSDC50_0_HCLK_SEL, + TOP_MSDC50_0_SEL, + TOP_MSDC30_1_SEL, + TOP_AUDIO_SEL, + TOP_AUD_INTBUS_SEL, + TOP_AUD_1_SEL, + TOP_AUD_2_SEL, + TOP_AUD_ENGEN1_SEL, + TOP_AUD_ENGEN2_SEL, + TOP_DISP_PWM_SEL, + TOP_SSPM_SEL, + TOP_DXCC_SEL, + TOP_USB_TOP_SEL, + TOP_SRCK_SEL, + TOP_SPM_SEL, + TOP_I2C_SEL, + TOP_PWM_SEL, + TOP_SENINF_SEL, + TOP_SENINF1_SEL, + TOP_SENINF2_SEL, + TOP_SENINF3_SEL, + TOP_AES_MSDCFDE_SEL, + TOP_PWRAP_ULPOSC_SEL, + TOP_CAMTM_SEL, + TOP_VENC_SEL, + TOP_CAM_SEL, + TOP_IMG1_SEL, + TOP_IPE_SEL, + TOP_DPMAIF_SEL, + TOP_VDEC_SEL, + TOP_DISP_SEL, + TOP_MDP_SEL, + TOP_AUDIO_H_SEL, + TOP_UFS_SEL, + TOP_AES_FDE_SEL, + TOP_AUDIODSP_SEL, + TOP_DVFSRC_SEL, + TOP_DSI_OCC_SEL, + TOP_SPMI_MST_SEL, + TOP_SPINOR_SEL, + TOP_NNA_SEL, + TOP_NNA1_SEL, + TOP_NNA2_SEL, + TOP_SSUSB_XHCI_SEL, + TOP_SSUSB_TOP_1P_SEL, + TOP_SSUSB_XHCI_1P_SEL, + TOP_WPE_SEL, + TOP_MEM_SEL, + TOP_DPI_SEL, + TOP_U3_OCC_250M_SEL, + TOP_U3_OCC_500M_SEL, + TOP_ADSP_BUS_SEL, + TOP_NR_MUX +}; + +#define MUX(_id, _reg, _mux_shift, _mux_width) \ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + } + +#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_reg##_set, \ + .clr_reg = &mtk_topckgen->_reg##_clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &mtk_topckgen->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +static const struct mux muxes[] = { + /* CLK_CFG_0 */ + MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 2, clk_cfg_update, 0), + MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 8, 3, clk_cfg_update, 1), + MUX_UPD(TOP_MFG_SEL, clk_cfg_0, 16, 2, clk_cfg_update, 2), + MUX_UPD(TOP_CAMTG_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3), + /* CLK_CFG_1 */ + MUX_UPD(TOP_CAMTG1_SEL, clk_cfg_1, 0, 3, clk_cfg_update, 4), + MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_1, 8, 3, clk_cfg_update, 5), + MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_1, 16, 3, clk_cfg_update, 6), + MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_1, 24, 3, clk_cfg_update, 7), + /* CLK_CFG_2 */ + MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_2, 0, 3, clk_cfg_update, 8), + MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_2, 8, 3, clk_cfg_update, 9), + MUX_UPD(TOP_UART_SEL, clk_cfg_2, 16, 1, clk_cfg_update, 10), + MUX_UPD(TOP_SPI_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11), + /* CLK_CFG_3 */ + MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_3, 0, 2, clk_cfg_update, 12), + MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13), + MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_3, 16, 3, clk_cfg_update, 14), + MUX_UPD(TOP_AUDIO_SEL, clk_cfg_3, 24, 2, clk_cfg_update, 15), + /* CLK_CFG_4 */ + MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_4, 0, 2, clk_cfg_update, 16), + MUX_UPD(TOP_AUD_1_SEL, clk_cfg_4, 8, 1, clk_cfg_update, 17), + MUX_UPD(TOP_AUD_2_SEL, clk_cfg_4, 16, 1, clk_cfg_update, 18), + MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_4, 24, 2, clk_cfg_update, 19), + /* CLK_CFG_5 */ + MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20), + MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21), + MUX_UPD(TOP_SSPM_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22), + MUX_UPD(TOP_DXCC_SEL, clk_cfg_5, 24, 2, clk_cfg_update, 23), + /* CLK_CFG_6 */ + MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_6, 0, 2, clk_cfg_update, 24), + MUX_UPD(TOP_SRCK_SEL, clk_cfg_6, 8, 2, clk_cfg_update, 25), + MUX_UPD(TOP_SPM_SEL, clk_cfg_6, 16, 2, clk_cfg_update, 26), + MUX_UPD(TOP_I2C_SEL, clk_cfg_6, 24, 2, clk_cfg_update, 27), + /* CLK_CFG_7 */ + MUX_UPD(TOP_PWM_SEL, clk_cfg_7, 0, 2, clk_cfg_update, 28), + MUX_UPD(TOP_SENINF_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29), + MUX_UPD(TOP_SENINF1_SEL, clk_cfg_7, 16, 2, clk_cfg_update, 30), + MUX_UPD(TOP_SENINF2_SEL, clk_cfg_7, 24, 2, clk_cfg_update1, 0), + /* CLK_CFG_8 */ + MUX_UPD(TOP_SENINF3_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1), + MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2), + MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 16, 3, clk_cfg_update1, 3), + MUX_UPD(TOP_CAMTM_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 4), + /* CLK_CFG_9 */ + MUX_UPD(TOP_VENC_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 5), + MUX_UPD(TOP_CAM_SEL, clk_cfg_9, 8, 4, clk_cfg_update1, 6), + MUX_UPD(TOP_IMG1_SEL, clk_cfg_9, 16, 4, clk_cfg_update1, 7), + MUX_UPD(TOP_IPE_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 8), + /* CLK_CFG_10 */ + MUX_UPD(TOP_DPMAIF_SEL, clk_cfg_10, 0, 3, clk_cfg_update1, 9), + MUX_UPD(TOP_VDEC_SEL, clk_cfg_10, 8, 3, clk_cfg_update1, 10), + MUX_UPD(TOP_DISP_SEL, clk_cfg_10, 16, 4, clk_cfg_update1, 11), + MUX_UPD(TOP_MDP_SEL, clk_cfg_10, 24, 4, clk_cfg_update1, 12), + /* CLK_CFG_11 */ + MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_11, 0, 2, clk_cfg_update1, 13), + MUX_UPD(TOP_UFS_SEL, clk_cfg_11, 8, 2, clk_cfg_update1, 14), + MUX_UPD(TOP_AES_FDE_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 15), + MUX_UPD(TOP_AUDIODSP_SEL, clk_cfg_11, 24, 3, clk_cfg_update1, 16), + /* CLK_CFG_12 */ + MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 18), + MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_12, 16, 3, clk_cfg_update1, 19), + /* CLK_CFG_13 */ + MUX_UPD(TOP_SPINOR_SEL, clk_cfg_13, 0, 3, clk_cfg_update1, 20), + MUX_UPD(TOP_NNA_SEL, clk_cfg_13, 7, 4, clk_cfg_update1, 21), + MUX_UPD(TOP_NNA1_SEL, clk_cfg_13, 15, 4, clk_cfg_update1, 22), + MUX_UPD(TOP_NNA2_SEL, clk_cfg_13, 23, 4, clk_cfg_update1, 23), + /* CLK_CFG_14 */ + MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_14, 0, 2, clk_cfg_update1, 24), + MUX_UPD(TOP_SSUSB_TOP_1P_SEL, clk_cfg_14, 6, 2, clk_cfg_update1, 25), + MUX_UPD(TOP_SSUSB_XHCI_1P_SEL, clk_cfg_14, 12, 2, clk_cfg_update1, 26), + MUX_UPD(TOP_WPE_SEL, clk_cfg_14, 18, 4, clk_cfg_update1, 27), + /* CLK_CFG_15 */ + MUX_UPD(TOP_DPI_SEL, clk_cfg_15, 0, 3, clk_cfg_update1, 28), + MUX_UPD(TOP_U3_OCC_250M_SEL, clk_cfg_15, 7, 1, clk_cfg_update1, 29), + MUX_UPD(TOP_U3_OCC_500M_SEL, clk_cfg_15, 12, 1, clk_cfg_update1, 30), + MUX_UPD(TOP_ADSP_BUS_SEL, clk_cfg_15, 17, 3, clk_cfg_update1, 31), +}; + +struct mux_sel { + enum mux_id id; + u32 sel; +}; + +static const struct mux_sel mux_sels[] = { + /* CLK_CFG_0 */ + { .id = TOP_AXI_SEL, .sel = 1 }, /* 1: mainpll_d7 */ + { .id = TOP_SCP_SEL, .sel = 3 }, /* 3: mainpll_d2_d2 */ + { .id = TOP_MFG_SEL, .sel = 1 }, /* 1: mfgpll_ck */ + { .id = TOP_CAMTG_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + /* CLK_CFG_1 */ + { .id = TOP_CAMTG1_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG2_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG3_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG4_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + /* CLK_CFG_2 */ + { .id = TOP_CAMTG5_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG6_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_SPI_SEL, .sel = 7 }, /* 7: mainpll_d5 */ + /* CLK_CFG_3 */ + { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ + { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ + { .id = TOP_MSDC30_1_SEL, .sel = 1 }, /* 1: msdcpll_d2 */ + { .id = TOP_AUDIO_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + /* CLK_CFG_4 */ + { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d2_d4 */ + { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */ + { .id = TOP_AUD_ENGEN1_SEL, .sel = 3 }, /* 3: apll1_d8 */ + /* CLK_CFG_5 */ + { .id = TOP_AUD_ENGEN2_SEL, .sel = 3 }, /* 3: apll2_d8 */ + { .id = TOP_DISP_PWM_SEL, .sel = 1 }, /* 1: univpll_d5_d2 */ + { .id = TOP_SSPM_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ + { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ + /* CLK_CFG_6 */ + { .id = TOP_USB_TOP_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_SRCK_SEL, .sel = 2 }, /* 2: ulposc1_d10 */ + { .id = TOP_SPM_SEL, .sel = 3 }, /* 3: mainpll_d7_d2 */ + { .id = TOP_I2C_SEL, .sel = 3 }, /* 3: univpll_d5_d2 */ + /* CLK_CFG_7 */ + { .id = TOP_PWM_SEL, .sel = 3 }, /* 3: univpll_d2_d4 */ + { .id = TOP_SENINF_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + { .id = TOP_SENINF1_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + { .id = TOP_SENINF2_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + /* CLK_CFG_8 */ + { .id = TOP_SENINF3_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + { .id = TOP_AES_MSDCFDE_SEL, .sel = 1 }, /* 1: univpll_d3 */ + { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d3_d2 */ + /* CLK_CFG_9 */ + { .id = TOP_VENC_SEL, .sel = 6 }, /* 6: mainpll_d3 */ + { .id = TOP_CAM_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */ + { .id = TOP_IMG1_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */ + { .id = TOP_IPE_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */ + /* CLK_CFG_10 */ + { .id = TOP_DPMAIF_SEL, .sel = 1 }, /* 1: univpll_d2_d2 */ + { .id = TOP_VDEC_SEL, .sel = 6 }, /* 6: univpll_d2_d2 */ + { .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mmpll_ck */ + { .id = TOP_MDP_SEL, .sel = 8 }, /* 8: mmpll_ck */ + /* CLK_CFG_11 */ + { .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */ + { .id = TOP_UFS_SEL, .sel = 1 }, /* 1: mainpll_d7 */ + { .id = TOP_AES_FDE_SEL, .sel = 1 }, /* 1: univpll_d3 */ + { .id = TOP_AUDIODSP_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_12 */ + { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d3_d2 */ + { .id = TOP_SPMI_MST_SEL, .sel = 2 }, /* 2: ulposc1_d4 */ + /* CLK_CFG_13 */ + { .id = TOP_SPINOR_SEL, .sel = 5 }, /* 5: mainpll_d7_d2 */ + { .id = TOP_NNA_SEL, .sel = 14 }, /* 14: nnapll_ck */ + { .id = TOP_NNA1_SEL, .sel = 14 }, /* 14: nnapll_ck */ + { .id = TOP_NNA2_SEL, .sel = 15 }, /* 15: nna2pll_ck */ + /* CLK_CFG_14 */ + { .id = TOP_SSUSB_XHCI_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_SSUSB_TOP_1P_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_SSUSB_XHCI_1P_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_WPE_SEL, .sel = 8 }, /* 8: mmpll_ck */ + /* CLK_CFG_15 */ + { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_ck */ + { .id = TOP_U3_OCC_250M_SEL, .sel = 1 }, /* 1: univpll_d5 */ + { .id = TOP_U3_OCC_500M_SEL, .sel = 1 }, /* 1: nna2pll_d2 */ + { .id = TOP_ADSP_BUS_SEL, .sel = 3 }, /* 3: mainpll_d2_d2 */ +}; + +enum pll_id { + APMIXED_ARMPLL_LL, + APMIXED_ARMPLL_BL, + APMIXED_CCIPLL, + APMIXED_MAINPLL, + APMIXED_UNIV2PLL, + APMIXED_MSDCPLL, + APMIXED_MMPLL, + APMIXED_NNAPLL, + APMIXED_NNA2PLL, + APMIXED_ADSPPLL, + APMIXED_MFGPLL, + APMIXED_TVDPLL, + APMIXED_APLL1, + APMIXED_APLL2, + APMIXED_PLL_MAX +}; + +static const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +static const struct pll plls[] = { + PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, + NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, + pll_div_rate), + PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con3, + NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, + pll_div_rate), + PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, + NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, + pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, + 23, 22, mainpll_con1, 24, mainpll_con1, 0, + pll_div_rate), + PLL(APMIXED_UNIV2PLL, univpll_con0, univpll_con3, + 23, 22, univpll_con1, 24, univpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, + NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, + NO_RSTB_SHIFT, 22, mmpll_con1, 24, mmpll_con1, 0, + pll_div_rate), + PLL(APMIXED_NNAPLL, nnapll_con0, nnapll_con3, + NO_RSTB_SHIFT, 22, nnapll_con1, 24, nnapll_con1, 0, + pll_div_rate), + PLL(APMIXED_NNA2PLL, nna2pll_con0, nna2pll_con3, + NO_RSTB_SHIFT, 22, nna2pll_con1, 24, nna2pll_con1, 0, + pll_div_rate), + PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, + NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, + pll_div_rate), + PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, + NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3, + NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_con4, + NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_con4, + NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, + pll_div_rate), +}; + +struct rate { + enum pll_id id; + u32 rate; +}; + +static const struct rate rates[] = { + { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, + { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, + { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, + { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, + { .id = APMIXED_UNIV2PLL, .rate = UNIV2PLL_HZ }, + { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, + { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, + { .id = APMIXED_NNAPLL, .rate = NNAPLL_HZ }, + { .id = APMIXED_NNA2PLL, .rate = NNA2PLL_HZ }, + { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, + { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, + { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ }, + { .id = APMIXED_APLL1, .rate = APLL1_HZ }, + { .id = APMIXED_APLL2, .rate = APLL2_HZ }, +}; + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + /* enable clock square */ + setbits32(&mtk_apmixed->ap_pll_con0, BIT(0)); + + udelay(PLL_CKSQ_ON_DELAY); + + /* enable clock square1 low-pass filter */ + setbits32(&mtk_apmixed->ap_pll_con0, BIT(1)); + + /* xPLL PWR ON */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].pwr_reg, PLL_PWR_ON); + + udelay(PLL_PWR_ON_DELAY); + + /* xPLL ISO Disable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + clrbits32(plls[i].pwr_reg, PLL_ISO); + + udelay(PLL_ISO_DELAY); + + /* disable glitch free if rate < 374MHz */ + for (i = 0; i < ARRAY_SIZE(rates); i++) { + if (rates[i].rate < 374 * MHz) + clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN); + } + + /* xPLL Frequency Set */ + for (i = 0; i < ARRAY_SIZE(rates); i++) + pll_set_rate(&plls[rates[i].id], rates[i].rate); + + /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); + + /* xPLL Frequency Enable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].reg, MT8186_PLL_EN); + + /* wait for PLL stable */ + udelay(PLL_EN_DELAY); + + /* xPLL DIV Enable & RSTB */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (plls[i].rstb_shift != NO_RSTB_SHIFT) { + setbits32(plls[i].reg, PLL_DIV_EN); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); + } + } + + /* MCUCFG CLKMUX */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL1_EN); + setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL2_EN); + + clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + + clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603); + write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603); + + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* [4] SCP_CORE_CK_CG, [5] SEJ_CG */ + write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030); + /* [7] DVFSRC_CG, [20] DEVICE_APC_CG */ + write32(&mt8186_infracfg_ao->module_sw_cg_1_clr, 0x00100080); + /* [15] SEJ_F13M_CK_CG, [16] AES_TOP0_BCLK_CK_CG */ + write32(&mt8186_infracfg_ao->module_sw_cg_3_clr, 0x00018000); +} + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable armpll_ll frequency output */ + clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch clock source back to armpll_ll */ + clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_raise_cci_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable ccipll frequency output */ + clrbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN); + + /* raise ccipll frequency */ + pll_set_rate(&plls[APMIXED_CCIPLL], freq); + + /* enable ccipll frequency output */ + setbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch clock source back to ccipll */ + clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) +{ + u32 output, count, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + clk26cali_0 = read32(&mtk_topckgen->clk26cali_0); + clk26cali_1 = read32(&mtk_topckgen->clk26cali_1); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 1); + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else { + die("unsupport fmeter type\n"); + } + + /* enable frequency meter */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_ENABLE, 1); + + /* trigger frequency meter */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1); + + /* wait frequency meter until finished */ + if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) { + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + output = (count * 26000) / 1024; /* KHz */ + } else { + output = 0; + } + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + write32(&mtk_topckgen->clk26cali_0, clk26cali_0); + write32(&mtk_topckgen->clk26cali_1, clk26cali_1); + + if (type == FMETER_ABIST) + return output * 2; + else if (type == FMETER_CKGEN) + return output; + + return 0; +} |