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| author | Raul E Rangel <rrangel@chromium.org> | 2021-07-23 16:43:18 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-04 10:34:34 +0000 |
| commit | cf17cd81d3e7f098fdef8d3af6f167409e1b157e (patch) | |
| tree | 8f47c59c0f0e4f0fb9fe316ae4e75af443daa98f | |
| parent | 6938f353cac958c82311f4fb126895cf3d7c519d (diff) | |
| download | coreboot-cf17cd81d3e7f098fdef8d3af6f167409e1b157e.tar.gz coreboot-cf17cd81d3e7f098fdef8d3af6f167409e1b157e.tar.bz2 coreboot-cf17cd81d3e7f098fdef8d3af6f167409e1b157e.zip | |
soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
AMD platforms require the destination buffer to be 64 byte aligned
when using the SPI DMA controller.
BUG=b:179699789
TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug
$1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0}
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
| -rw-r--r-- | src/soc/amd/common/block/lpc/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index e7756069100f..76f4ec7ac3ab 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -16,6 +16,12 @@ config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA help Select this option to enable SPI DMA support. +# The LPC SPI DMA controller requires the destination buffers to be 64 byte +# aligned. +config CBFS_CACHE_ALIGN + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help |