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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-03 05:20:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-04 04:51:37 +0000 |
| commit | f9014bbb60b1a4fdfd7aad90579f01dd8e42b1bc (patch) | |
| tree | 205323f7db226685e5788c221af348ad2c30537e | |
| parent | 26806aed5cd27d4985e29a141d98e8c20add6fd9 (diff) | |
| download | coreboot-f9014bbb60b1a4fdfd7aad90579f01dd8e42b1bc.tar.gz coreboot-f9014bbb60b1a4fdfd7aad90579f01dd8e42b1bc.tar.bz2 coreboot-f9014bbb60b1a4fdfd7aad90579f01dd8e42b1bc.zip | |
mb/google/guybrush/bootblock: add comment on selecting eSPI interface
Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the
eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 83ac43ac4175..187b2ef953d2 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -63,6 +63,7 @@ void bootblock_mainboard_early_init(void) /* Early eSPI interface configuration */ + /* Use SPI2 pins for eSPI */ dword = pm_read32(PM_SPI_PAD_PU_PD); dword |= PM_ESPI_CS_USE_DATA2; pm_write32(PM_SPI_PAD_PU_PD, dword); |