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| author | Sean Rhodes <sean@starlabs.systems> | 2022-02-16 16:50:55 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 17:10:37 +0000 |
| commit | 3a260ad8f15deddbac3fd37238be87d85797e053 (patch) | |
| tree | cb7f886bb1657ef1bf38ff201028c6c62946a07c | |
| parent | 532e043b66a6f05ba2d8a73b431913295ed89f11 (diff) | |
| download | coreboot-3a260ad8f15deddbac3fd37238be87d85797e053.tar.gz coreboot-3a260ad8f15deddbac3fd37238be87d85797e053.tar.bz2 coreboot-3a260ad8f15deddbac3fd37238be87d85797e053.zip | |
soc/apollolake: Allow configuring individual USB ports on GLK
Allow configuring the limited fields that FSP-S provides.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 82ec2da4536d..fdc5fcc41936 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -536,7 +536,18 @@ static void glk_fsp_silicon_init_params_cb( #if CONFIG(SOC_INTEL_GEMINILAKE) uint8_t port; + /* + * UsbPerPortCtl was retired in Fsp 2.0.0+, so PDO programming must be + * enabled to configure individual ports in what Fsp thinks is PEI. + */ + silconfig->UsbPdoProgramming = cfg->usb_config_override; + for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { + if (cfg->usb_config_override) { + silconfig->PortUsb20Enable[port] = cfg->usb2_port[port].enable; + silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin; + } + if (!cfg->usb2eye[port].Usb20OverrideEn) continue; @@ -550,6 +561,13 @@ static void glk_fsp_silicon_init_params_cb( cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; } + if (cfg->usb_config_override) { + for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) { + silconfig->PortUsb30Enable[port] = cfg->usb3_port[port].enable; + silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin; + } + } + silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM); /* On Geminilake, we need to override the default FSP PCIe de-emphasis |