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| author | Reka Norman <rekanorman@google.com> | 2022-02-16 10:12:36 +1100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-21 17:05:45 +0000 |
| commit | 5bba93e08ae8759592efae65617e6d2ea26b73e7 (patch) | |
| tree | af0fef8f0c4e226751a30a0bafbd46f08220f5f3 | |
| parent | aade40c3f6b9dc40510932baceeb4374fd6c6ee6 (diff) | |
| download | coreboot-5bba93e08ae8759592efae65617e6d2ea26b73e7.tar.gz coreboot-5bba93e08ae8759592efae65617e6d2ea26b73e7.tar.bz2 coreboot-5bba93e08ae8759592efae65617e6d2ea26b73e7.zip | |
mb/google/brya: Enable eMMC HS400 mode for nissa
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 74b24c8581c0..91c633a3faf6 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -17,6 +17,9 @@ chip soc/intel/alderlake # Enable CNVi BT register "CnviBtCore" = "true" + # eMMC HS400 + register "emmc_enable_hs400_mode" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 |