soc/intel/skylake: Enable CIO depending on devicetree configuration

Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.

All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.

Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

19 files changed, 18 insertions, 21 deletions

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index b3d9929e2b65..294ae440221f 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -49,7 +49,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -125,6 +124,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index bede4e325ef5..6078741b705f 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
-	register "Cio2Enable" = "0"
 	register "PmTimerDisabled" = "1"
 	register "HeciEnabled" = "0"
 
@@ -243,6 +242,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 17.0 on  end # SATA
 		device pci 1c.2 on  end # PCI Express Port 3 x1 baseboard WWAN
 		device pci 1c.5 on  end # PCI Express Port 6 x1 baseboard i210
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 8d15e8e50df8..b42d917a3de9 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -42,7 +42,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -295,6 +294,7 @@ chip soc/intel/skylake
 		end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index e8412d5ce015..5faf760ac926 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -73,7 +73,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -376,6 +375,7 @@ chip soc/intel/skylake
 		end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 off end # I2C #1
 		device pci 15.2 on  end # I2C #2
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 108470bf9240..98b678a5cf24 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -104,6 +103,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 94861473b9e2..ce725f6ba878 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -274,6 +273,7 @@ chip soc/intel/skylake
 		end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 on  end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""ACPI0C50""
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index e672940f3c82..3197288573b3 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -270,6 +269,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 on  end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 7ee311699baa..57444a92a536 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -37,7 +37,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -285,6 +284,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0001""
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index c45434867263..025b82b70af2 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -291,6 +290,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 on  end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""SYTS7813""
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index aef571a9fcf0..3606ae21d581 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -43,7 +43,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -298,6 +297,7 @@ chip soc/intel/skylake
 		end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 on  end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOM50C1""
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index d21f98474af3..3587cda4be03 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -282,6 +281,7 @@ chip soc/intel/skylake
 		end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PNP0C50""
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 64ef50153657..2bddae2692be 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -271,6 +270,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 on  end # Camera
 		device pci 15.0 on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WCOMCOHO""
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index fe5edbe9b9cf..4bcfc9908311 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -9,7 +9,6 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "DspEnable" = "1"
 	register "PmTimerDisabled" = "1"
-	register "Cio2Enable" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
@@ -121,6 +120,7 @@ chip soc/intel/skylake
 
 	device domain 0 on
 		device pci 05.0 on  end # SA IMGU
+		device pci 14.3 on  end # Camera
 		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
 		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
 		device pci 1c.5 on  end # PCI Express Port 6 x1 SLOT3
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index 91552a26b867..d47eca8a48a8 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -50,7 +50,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "0"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "HeciEnabled" = "1"
@@ -176,6 +175,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index f0759efa9027..a5b363822021 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "HeciEnabled" = "1"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 60f69c811007..23c57120f1e5 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -55,7 +55,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -173,6 +172,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 6217de509743..edf13335a23c 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "SsicPortEnable" = "0"
-	register "Cio2Enable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -192,6 +191,7 @@ chip soc/intel/skylake
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
+		device pci 14.3 off end # Camera
 		device pci 15.0 on  end # I2C Controller #0
 		device pci 15.1 on
 			chip drivers/i2c/hid
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 80e89f6cce21..9239fd24de57 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -229,7 +229,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
 	       sizeof(params->SerialIoDevMode));
 
-	params->PchCio2Enable = config->Cio2Enable;
+	dev = pcidev_path_on_root(PCH_DEVFN_CIO);
+	params->PchCio2Enable = dev && dev->enabled;
 
 	dev = pcidev_path_on_root(SA_DEVFN_IMGU);
 	params->SaImguEnable = dev && dev->enabled;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 33fe52c2b60d..b1cf4dcb9bbd 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -300,9 +300,6 @@ struct soc_intel_skylake_config {
 	/* Bus voltage level, default is 3.3V */
 	enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 
-	/* Camera */
-	u8 Cio2Enable;
-
 	/* eMMC and SD */
 	u8 ScsEmmcHs400Enabled;
 	u8 EmmcHs400DllNeed;