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| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2022-02-21 19:32:39 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 00:32:24 +0000 |
| commit | e39d371909ff6ac6968b63cfc945338212c9a1c4 (patch) | |
| tree | e99457b5650ddfddb222579ae90711dc1cab2c73 | |
| parent | 77711b86778bd31acd866bfbc979ebab3708399a (diff) | |
| download | coreboot-e39d371909ff6ac6968b63cfc945338212c9a1c4.tar.gz coreboot-e39d371909ff6ac6968b63cfc945338212c9a1c4.tar.bz2 coreboot-e39d371909ff6ac6968b63cfc945338212c9a1c4.zip | |
mb/google/brya/var/vell: Corrects ACPI _PLD macro setting
This patch is to denote the correct side of ACPI _PLD usb C ports.
+-------------------------+
| LCD |
| |
| |
+-------------------------+
PORT_C2 | | PORT_C1
PORT_C3 | DB MB | PORT_C0
| |
+-------------------------+
BUG=b:220634230
TEST=emerge-brya coreboot
Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 9250dc65ca76..690e2669db2e 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -364,28 +364,28 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (MlB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C3 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref tcss_usb3_port4 on end end end @@ -398,21 +398,21 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -424,7 +424,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C3 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port5 on end end chip drivers/usb/acpi |