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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-10-13 16:16:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 15:36:40 +0000 |
| commit | 2595946bcd40ef9dd7526eb48c19ca6c90786c2e (patch) | |
| tree | fb372cba28c56458db5860532211e281be8dd015 | |
| parent | 26651c85a03bbe09e17d0e17757c882dae404ebd (diff) | |
| download | coreboot-2595946bcd40ef9dd7526eb48c19ca6c90786c2e.tar.gz coreboot-2595946bcd40ef9dd7526eb48c19ca6c90786c2e.tar.bz2 coreboot-2595946bcd40ef9dd7526eb48c19ca6c90786c2e.zip | |
soc/amd/stoneyridge: move northbridge ops to northbridge device
The northbridge ops should be added to the actual northbridge and not
the first HT device. Neither of the devices has BARs on it, so
read_resources implementation will still work correctly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e5f21bfe5fff043d7d9afafa360764203dd61f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68409
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/chipset_cz.cb | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/chipset_st.cb | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/chipset_cz.cb b/src/soc/amd/stoneyridge/chipset_cz.cb index 54acf2a07581..31b4a4db5d88 100644 --- a/src/soc/amd/stoneyridge/chipset_cz.cb +++ b/src/soc/amd/stoneyridge/chipset_cz.cb @@ -6,7 +6,7 @@ chip soc/amd/stoneyridge end device domain 0 on ops stoneyridge_pci_domain_ops - device pci 00.0 alias gnb on end + device pci 00.0 alias gnb on ops stoneyridge_northbridge_operations end device pci 00.2 alias iommu off end device pci 01.0 alias gfx off end # internal GPU device pci 01.1 alias gfx_hda off end # display HD Audio controller @@ -31,7 +31,7 @@ chip soc/amd/stoneyridge device pci 14.0 alias smbus on end # primary FCH function device pci 14.3 alias lpc_bridge on end device pci 14.7 alias sdhci off end - device pci 18.0 alias ht_0 on ops stoneyridge_northbridge_operations end + device pci 18.0 alias ht_0 on end device pci 18.1 alias ht_1 on end device pci 18.2 alias ht_2 on end device pci 18.3 alias ht_3 on end diff --git a/src/soc/amd/stoneyridge/chipset_st.cb b/src/soc/amd/stoneyridge/chipset_st.cb index be630d963fef..3544ea82671f 100644 --- a/src/soc/amd/stoneyridge/chipset_st.cb +++ b/src/soc/amd/stoneyridge/chipset_st.cb @@ -6,7 +6,7 @@ chip soc/amd/stoneyridge end device domain 0 on ops stoneyridge_pci_domain_ops - device pci 00.0 alias gnb on end + device pci 00.0 alias gnb on ops stoneyridge_northbridge_operations end device pci 00.2 alias iommu off end device pci 01.0 alias gfx off end # internal GPU device pci 01.1 alias gfx_hda off end # display HD Audio controller @@ -25,7 +25,7 @@ chip soc/amd/stoneyridge device pci 14.0 alias smbus on end # primary FCH function device pci 14.3 alias lpc_bridge on end device pci 14.7 alias sdhci off end - device pci 18.0 alias ht_0 on ops stoneyridge_northbridge_operations end + device pci 18.0 alias ht_0 on end device pci 18.1 alias ht_1 on end device pci 18.2 alias ht_2 on end device pci 18.3 alias ht_3 on end |