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| author | Caesar Wang <wxt@rock-chips.com> | 2017-05-16 08:39:40 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-05-18 00:13:23 +0200 |
| commit | 2684efc49213802dcd36bd9bddd7a69851b8774a (patch) | |
| tree | 818c698fc13fff5cd733b242fbde2fd9fc8594a8 | |
| parent | c7ccb6b29fb138b1d5f6ac6f702e9e378f71e2d7 (diff) | |
| download | coreboot-2684efc49213802dcd36bd9bddd7a69851b8774a.tar.gz coreboot-2684efc49213802dcd36bd9bddd7a69851b8774a.tar.bz2 coreboot-2684efc49213802dcd36bd9bddd7a69851b8774a.zip | |
rockchip/rk3399: remove the delay for enabling SSC
The hang was caused by deasserting the reset before, it had been delayed 20us
fixing the hang issue.
So we can remove this delay for now.
Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 944ca6f4175c..7e205d2ba4bb 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -356,11 +356,6 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) { u32 divval; - /* - * TODO find the root cause why is the delay needed, otherwise sometimes - * hang somewhere with reboot tests. - */ - udelay(30); assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6); /* |