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| author | Zhixing Ma <zhixing.ma@intel.com> | 2022-09-30 14:18:13 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 15:58:46 +0000 |
| commit | 30e8fc1f4e7d4e79b1403acd3679ce08598687c3 (patch) | |
| tree | 763280274a4656aebde3bc8f2a38ccc154717047 | |
| parent | eb3532768198c71b39c28c36769b04d2b8176bca (diff) | |
| download | coreboot-30e8fc1f4e7d4e79b1403acd3679ce08598687c3.tar.gz coreboot-30e8fc1f4e7d4e79b1403acd3679ce08598687c3.tar.bz2 coreboot-30e8fc1f4e7d4e79b1403acd3679ce08598687c3.zip | |
soc/intel/alderlake: Fix unknown voltage in SMBIOS
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements voltage function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor voltage value is correct.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index ca0af8a8609f..1474ce84a24d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -76,6 +76,7 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_2 select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON + select CPU_INTEL_COMMON_VOLTAGE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI |