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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-10-15 17:17:09 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:19:23 +0100 |
| commit | d5855ec5326f7696a22e0da776a63cc350c2dd16 (patch) | |
| tree | 626297818fb081a4024ad1c74830710b5b4bbf0f | |
| parent | 66208bd3d5203ccaf052c3e3663df702d367e4a7 (diff) | |
| download | coreboot-d5855ec5326f7696a22e0da776a63cc350c2dd16.tar.gz coreboot-d5855ec5326f7696a22e0da776a63cc350c2dd16.tar.bz2 coreboot-d5855ec5326f7696a22e0da776a63cc350c2dd16.zip | |
FSP1_1: Always use common code
Always use the common FSP code. Remove the FSP_RAM_INIT, FSP_ROMSTAGE,
FSP_STACK and FSP_STAGE_CACHE Kconfig values.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: Ib3d015cb2dc257e46c2340cc7bc09cf0ffb0492c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5197b1354d138759dfaa428c665de6cbfb8e8911
Original-Change-Id: I3e3c1c9e6f73009a099c1ec3688dbd8c326fc766
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306142
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12158
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
| -rw-r--r-- | src/drivers/intel/fsp1_1/Kconfig | 17 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/Makefile.inc | 10 | ||||
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 4 |
4 files changed, 5 insertions, 30 deletions
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index d0683370e82c..1e1ef18bebd1 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -116,22 +116,6 @@ config DISPLAY_UPD_DATA Display the user specified product data prior to memory initialization. -config FSP_RAM_INIT - bool - default n - -config FSP_ROMSTAGE - bool - default n - -config FSP_STACK - bool - default n - -config FSP_STAGE_CACHE - bool - default n - config FSP_USES_UPD bool default n @@ -146,7 +130,6 @@ config GOP_SUPPORT config ROMSTAGE_RAM_STACK_SIZE hex "Size of the romstage RAM stack in bytes" default 0x5000 - depends on FSP_STACK config USE_GENERIC_FSP_CAR_INC bool diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 19bee827e57b..bf8f6a9f96c9 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -25,18 +25,18 @@ verstage-y += verstage.c romstage-y += car.c romstage-y += fsp_util.c romstage-y += hob.c -romstage-$(CONFIG_FSP_RAM_INIT) += raminit.c -romstage-$(CONFIG_FSP_ROMSTAGE) += romstage.c +romstage-y += raminit.c +romstage-y += romstage.c romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S -romstage-$(CONFIG_FSP_STACK) += stack.c -romstage-$(CONFIG_FSP_STAGE_CACHE) += stage_cache.c +romstage-y += stack.c +romstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c ramstage-y += fsp_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c ramstage-y += ramstage.c -ramstage-$(CONFIG_FSP_STAGE_CACHE) += stage_cache.c +ramstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index e6f22755adc7..11d946aa27bc 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -17,10 +17,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select FSP_RAM_INIT - select FSP_ROMSTAGE - select FSP_STACK - select FSP_STAGE_CACHE select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d63fa70d9a35..b67faab923a1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -19,10 +19,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS - select FSP_RAM_INIT - select FSP_ROMSTAGE - select FSP_STACK - select FSP_STAGE_CACHE select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_HARD_RESET |