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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> | 2022-10-12 00:05:41 -0700 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-05-11 08:18:39 +0000 |
| commit | 31e0aeb74778a836636573952a40c847686ef69d (patch) | |
| tree | e5eded36fafad1afc820774a75e3cd82ed7df44d | |
| parent | d4a7dceaa589d2be44a13fc5e188ec523b1618a7 (diff) | |
| download | coreboot-31e0aeb74778a836636573952a40c847686ef69d.tar.gz coreboot-31e0aeb74778a836636573952a40c847686ef69d.tar.bz2 coreboot-31e0aeb74778a836636573952a40c847686ef69d.zip | |
soc/intel/meteorlake: Increase pcie snoop/non-snoop latency
This fixes an issue where pcie was not power gating and blocked
S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance
values to 15.73ms as stated in doc #729123 - MTL External Design
Specification.
BUG=none
TEST=Boot google/rex, print/check values.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index ee29b508496f..311f636d1add 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -385,4 +385,16 @@ config DROP_CPU_FEATURE_PROGRAM_IN_FSP This feature is default enabled, in case of "coreboot running MP init" aka MP_SERVICES_PPI_V2_NOOP config is selected. +config PCIE_LTR_MAX_SNOOP_LATENCY + hex + default 0x100f + help + Latency tolerance reporting, max snoop latency value defaults to 15.73 ms. + +config PCIE_LTR_MAX_NO_SNOOP_LATENCY + hex + default 0x100f + help + Latency tolerance reporting, max non-snoop latency value defaults to 15.73 ms. + endif |