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authorSean Rhodes <sean@starlabs.systems>2022-05-19 15:35:31 +0100
committerNico Huber <nico.h@gmx.de>2022-06-20 20:09:40 +0000
commit57779955c9be64426e591557fe8571637028ddad (patch)
tree24503f839e3593236d4d8900abd9a5556b1bbd2a
parent3f205a416e89b3a105a5346fa2381b1675e859e5 (diff)
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soc/intel/apollolake: Hook Up SataPortEnable to devicetree
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat
-rw-r--r--src/mainboard/intel/apollolake_rvp/devicetree.cb5
-rw-r--r--src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb5
-rw-r--r--src/mainboard/intel/leafhill/devicetree.cb5
-rw-r--r--src/mainboard/intel/minnow3/devicetree.cb5
-rw-r--r--src/mainboard/kontron/mal10/variants/mal10/devicetree.cb5
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb2
-rw-r--r--src/mainboard/starlabs/lite/variants/glk/devicetree.cb5
-rw-r--r--src/mainboard/starlabs/lite/variants/glkr/devicetree.cb5
-rw-r--r--src/mainboard/up/squared/devicetree.cb5
-rw-r--r--src/soc/intel/apollolake/chip.c5
-rw-r--r--src/soc/intel/apollolake/chip.h3
16 files changed, 51 insertions, 9 deletions
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index dd12a5b8c330..5421dc32621e 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -24,7 +24,10 @@ chip soc/intel/apollolake
device pci 0e.0 on end # - Audio
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
- device pci 12.0 on end # - SATA
+ device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 on end # - PCIe-A 0
device pci 13.2 on end # - Onboard Lan
device pci 13.3 on end # - PCIe-A 3
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index f025d1fd0a93..6ab391e36b52 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -124,7 +124,10 @@ chip soc/intel/apollolake
device pci 0f.1 on end # - Heci2
device pci 0f.2 on end # - Heci3
device pci 11.0 off end # - ISH
- device pci 12.0 on end # - SATA
+ device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 off end # - PCIe-A 0 Slot 1
device pci 13.1 off end # - PCIe-A 1
device pci 13.2 off end # - PCIe-A 2 Onboard Lan
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index e2f2f8e5599c..76362e663e2b 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -24,7 +24,10 @@ chip soc/intel/apollolake
device pci 0e.0 on end # - Audio
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
- device pci 12.0 on end # - SATA
+ device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 on end # - PCIe-A 0
device pci 13.2 on end # - Onboard Lan
device pci 13.3 on end # - PCIe-A 3
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index e2f2f8e5599c..76362e663e2b 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -24,7 +24,10 @@ chip soc/intel/apollolake
device pci 0e.0 on end # - Audio
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
- device pci 12.0 on end # - SATA
+ device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 on end # - PCIe-A 0
device pci 13.2 on end # - Onboard Lan
device pci 13.3 on end # - PCIe-A 3
diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
index 5c89a644d999..20089df1b619 100644
--- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
+++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
@@ -21,7 +21,10 @@ chip soc/intel/apollolake
device pci 0e.0 on end # Audio
device pci 0f.0 on end # TXE
device pci 11.0 off end # ISH
- device pci 12.0 on end # SATA
+ device pci 12.0 on # SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 on # PCIe-A 1 (Root Port 2)
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
end
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 0d1cc46c11c8..bb978f4dfee6 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -73,6 +73,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index 6c17d6329870..f1594d2b7748 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -71,6 +71,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index 449230f44bd5..e6e14cb16a0e 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -68,6 +68,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index 58791f3f10ea..c601106c5e04 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -52,6 +52,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index c4c2e3df9a15..e2d2606a84da 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -71,6 +71,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index f75dc1cd863c..27b3b93b6ed4 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -42,6 +42,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
end
device pci 13.0 on # - RP 2 - PCIe A 0
diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
index 1c23eec44d85..303ba5ff5b1e 100644
--- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
@@ -78,7 +78,10 @@ chip soc/intel/apollolake
device pci 0f.1 on end # Heci2
device pci 0f.2 on end # Heci3
device pci 11.0 off end # ISH
- device pci 12.0 on end # SATA
+ device pci 12.0 on # SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 off end # PCIe-A 0 Slot 1
device pci 13.1 off end # PCIe-A 1
device pci 13.2 off end # PCIe-A 2 Onboard Lan
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
index aad20ea8f664..150ab57d4796 100644
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -78,7 +78,10 @@ chip soc/intel/apollolake
device pci 0f.1 on end # Heci2
device pci 0f.2 on end # Heci3
device pci 11.0 off end # ISH
- device pci 12.0 on end # SATA
+ device pci 12.0 on # SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 off end # PCIe-A 0 Slot 1
device pci 13.1 off end # PCIe-A 1
device pci 13.2 off end # PCIe-A 2 Onboard Lan
diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb
index 9ed998587005..128c1bba4544 100644
--- a/src/mainboard/up/squared/devicetree.cb
+++ b/src/mainboard/up/squared/devicetree.cb
@@ -37,7 +37,10 @@ chip soc/intel/apollolake
device pci 0e.0 on end # - Audio
device pci 0f.0 on end # - TXE
device pci 11.0 off end # - ISH
- device pci 12.0 on end # - SATA
+ device pci 12.0 on # - SATA
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ end
device pci 13.0 on end # - PCIe-A 1 - PcieRootPort[2]
device pci 13.1 on end # - PCIe-A 2 - PcieRootPort[3]
device pci 13.2 on end # - PCIe-A 3 - PcieRootPort[4]
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index e8243283500d..ac8dfdf568d5 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -728,8 +728,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->PavpEnable = CONFIG(PAVP);
/* SATA config */
- if (is_devfn_enabled(PCH_DEVFN_SATA))
+ if (is_devfn_enabled(PCH_DEVFN_SATA)) {
silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport);
+ memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable,
+ sizeof(silconfig->SataPortsEnable));
+ }
/* 8254 Timer */
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index de3ba9780c1c..c220453595fc 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -99,6 +99,9 @@ struct soc_intel_apollolake_config {
/* Sata Ports Hot Plug */
uint8_t SataPortsHotPlug[2];
+ /* Sata Ports Enable */
+ uint8_t SataPortsEnable[2];
+
/* Specifies on which IRQ the SCI will internally appear. */
uint8_t sci_irq;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 04:43:04 +0000