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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-09 09:49:13 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-11 16:48:15 +0000 |
| commit | 7ad8b0987ac6f3438b209ce2c6d3bd16a5c93f21 (patch) | |
| tree | 65b13a09ac51d7ed11ef961c4ad2854e22b5b29a | |
| parent | 08706a3ad03cf9005c788451f93a4f7b5508720f (diff) | |
| download | coreboot-7ad8b0987ac6f3438b209ce2c6d3bd16a5c93f21.tar.gz coreboot-7ad8b0987ac6f3438b209ce2c6d3bd16a5c93f21.tar.bz2 coreboot-7ad8b0987ac6f3438b209ce2c6d3bd16a5c93f21.zip | |
mb/siemens/mc_apl5: Set Full Reset Bit into Reset Control Register
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ia8b7f997ca6234add569da751e1070144790e258
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index d01d5470967d..7362a486d0c1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> +#include <cf9_reset.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -59,6 +60,11 @@ void variant_mainboard_final(void) if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x3e); } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 + and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is + then used on the mainboard to generate the right reset timing. */ + outb(FULL_RST, RST_CNT); } static void finalize_boot(void *unused) |