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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-04-18 18:51:38 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-13 17:22:16 +0000 |
| commit | bba14fe497be6b45f570e04049f95b5908843ae5 (patch) | |
| tree | 95f6ce7c5a904d38835bc4185d8d8f1dc445e04d | |
| parent | 1443137d5ca8b444f26ce5d4710785d933a2a26b (diff) | |
| download | coreboot-bba14fe497be6b45f570e04049f95b5908843ae5.tar.gz coreboot-bba14fe497be6b45f570e04049f95b5908843ae5.tar.bz2 coreboot-bba14fe497be6b45f570e04049f95b5908843ae5.zip | |
soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register
Clang complains about this.
Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/cavium/cn81xx/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index 43b64d543017..9ed20d09d7c0 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -35,7 +35,7 @@ void secondary_cpu_init(size_t core_id) size_t cpu_self_get_core_id(void) { - u32 mpidr_el1; + u64 mpidr_el1; asm("mrs %0, MPIDR_EL1\n\t" : "=r" (mpidr_el1) :: "memory"); /* Core is 4 bits from AFF0 and rest from AFF1 */ |