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| author | Julius Werner <jwerner@chromium.org> | 2023-11-16 16:26:45 -0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2023-11-18 00:41:53 +0000 |
| commit | 653f349f2fcaaf12a566c642acb88a23b1804c01 (patch) | |
| tree | f62676aafdfce6b0d1db7651e29ab275ff7a75ef | |
| parent | 947eebedcb34c59ecf46088d3ca57b4ad3c35a9b (diff) | |
| download | coreboot-653f349f2fcaaf12a566c642acb88a23b1804c01.tar.gz coreboot-653f349f2fcaaf12a566c642acb88a23b1804c01.tar.bz2 coreboot-653f349f2fcaaf12a566c642acb88a23b1804c01.zip | |
qualcomm/sc7180: Move QCSDI and increase romstage size by 4KB
We need to increase romstage size a little to make a compiler upgrade
fit (CB:70771). Unfortunately the end of the romstage directly touches
the QCSDI region in the current memlayout, and there is no other way
to reshuffle things to make more space... so we need to move QCSDI out
of the way. This means that anyone who is actually building this
platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob
that's not publicly available) will need to recompile their QCSDI binary
to match the new start address.
Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
| -rw-r--r-- | src/soc/qualcomm/sc7180/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index e956c647ff56..adc9a0b0f9e2 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -23,8 +23,8 @@ SECTIONS AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 100K) - REGION(qcsdi, 0x14699000, 52K, 4K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 104K) + REGION(qcsdi, 0x1469E000, 55K, 4K) REGION(modem_id, 0x146ABD00, 4, 4) SSRAM_END(0x146AE000) |