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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-16 00:58:30 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-17 16:28:10 +0000 |
| commit | 8ccd314ce6b954a93528897fb029e66bf6078bd8 (patch) | |
| tree | 8cfd4a3b0d3a780b664a922b30440b995cae3b2e | |
| parent | 1952d13a414229f1867a8a9c00fc07df07d7042c (diff) | |
| download | coreboot-8ccd314ce6b954a93528897fb029e66bf6078bd8.tar.gz coreboot-8ccd314ce6b954a93528897fb029e66bf6078bd8.tar.bz2 coreboot-8ccd314ce6b954a93528897fb029e66bf6078bd8.zip | |
nb/amd/pi/00730F01: add CPU and domain ops in devicetree
Add the CPU and PCI domain operation bindings statically in the chipset
devicetree instead of adding them during runtime.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/chipset.cb | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 15 |
2 files changed, 6 insertions, 14 deletions
diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index 57f89c487075..bc794262c996 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -1,9 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01 - device cpu_cluster 0 on end + device cpu_cluster 0 on + ops amd_fam16_mod30_cpu_bus_ops + end device domain 0 on + ops amd_fam16_mod30_pci_domain_ops device pci 0.0 alias gnb on end device pci 0.2 alias iommu off end device pci 1.0 alias gfx off end diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e8f7abdc3134..3ac94e5d2a1b 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -831,7 +831,7 @@ static const char *domain_acpi_name(const struct device *dev) return NULL; } -static struct device_operations pci_domain_ops = { +struct device_operations amd_fam16_mod30_pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_host_bridge_scan_bus, @@ -863,26 +863,15 @@ void generate_cpu_entries(const struct device *device) } } -static struct device_operations cpu_bus_ops = { +struct device_operations amd_fam16_mod30_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; -static void root_complex_enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - struct chip_operations northbridge_amd_pi_00730F01_ops = { CHIP_NAME("AMD FAM16 Root Complex") - .enable_dev = root_complex_enable_dev, .final = fam16_finalize, }; |