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authorMartin Roth <gaumless@gmail.com>2023-11-08 18:18:11 -0700
committerFelix Held <felix-coreboot@felixheld.de>2023-11-10 15:27:45 +0000
commit6fd7f112250f495e73e650bf07b2597274676cc8 (patch)
treea6f9bd51b83d158290230ffb3e7d4079130a48f0
parentd205cf7e4ef6ebec49d45ec97f501f7de843ac94 (diff)
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src: Remove unnecessary semicolons from the end of macros
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia005915a05d02725f77b52ccd7acebefaf25d058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78964 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/arch/arm64/include/armv8/arch/barrier.h2
-rw-r--r--src/include/cpu/intel/l2_cache.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h
index 2be2bd3c83fd..00b9b6219a22 100644
--- a/src/arch/arm64/include/armv8/arch/barrier.h
+++ b/src/arch/arm64/include/armv8/arch/barrier.h
@@ -24,7 +24,7 @@
#define barrier() __asm__ __volatile__("" : : : "memory")
#endif
-#define nop() asm volatile("nop");
+#define nop() asm volatile("nop")
#define force_read(x) (*(volatile typeof(x) *)&(x))
diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h
index a859dfaf1edc..7d256b4c06ed 100644
--- a/src/include/cpu/intel/l2_cache.h
+++ b/src/include/cpu/intel/l2_cache.h
@@ -44,7 +44,7 @@
#define BBLCR3_L2_SIZE_2M (0x08 << 13)
#define BBLCR3_L2_SIZE_4M (0x10 << 13)
/* bits [22:20] */
-#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20);
+#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20)
/* TODO: This bitmask does not agree with Intel's documentation.
* Get confirmation one way or another.
*/