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authorKangheui Won <khwon@chromium.org>2020-04-21 17:55:53 +1000
committerPatrick Georgi <pgeorgi@google.com>2020-04-22 13:48:22 +0000
commitb8d083ec74735b50917adfc2b4da41e3ac698ad3 (patch)
tree02e88317972629a08b47b20394a8bb6c3aa0dc80
parent9138eee4f7ed304a27fcb0028dd8865d79537374 (diff)
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mb/google/puff: comment schematics changes for USB
USB routing has changed on reference schematics after Puff rev1 has built. This may confuse people trying to c&p devicetree from the Puff. So add comment to clearly note that there was change, hopefully preventing c&p errors. BUG=b:153682207 BRANCH=None TEST=None Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I5c43a5c04c81b6708c9eeabc48ef11961d7c8561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40546 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/hatch/variants/puff/overridetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 2f36bc8b62c8..d869b28a336d 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -21,6 +21,9 @@ chip soc/intel/cannonlake
}"
# USB configuration
+ # NOTE: This only applies to Puff,
+ # usb2_ports[1] and usb2_ports[3] were swapped on
+ # reference schematics after Puff has been built.
register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[2]" = "{