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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-17 17:50:40 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-24 19:45:04 +0200 |
| commit | 00fd3ff507568d93cc1fb4e3c9d6742cde58fae0 (patch) | |
| tree | a37a9c636a1cfc9d85082df9f70dfbed3d7cebba | |
| parent | 5e1194567f182e58eebd4d00370f0389a8c12b37 (diff) | |
| download | coreboot-00fd3ff507568d93cc1fb4e3c9d6742cde58fae0.tar.gz coreboot-00fd3ff507568d93cc1fb4e3c9d6742cde58fae0.tar.bz2 coreboot-00fd3ff507568d93cc1fb4e3c9d6742cde58fae0.zip | |
nb/pineview/raminit: Fix raminit failing on hot reset path
For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19337
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/intel/d510mo/romstage.c | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/raminit.c | 24 |
2 files changed, 22 insertions, 7 deletions
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 3209d81ed1dc..d39d2f654262 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -121,7 +121,10 @@ void mainboard_romstage_entry(unsigned long bist) post_code(0x30); printk(BIOS_DEBUG, "Initializing memory\n"); - sdram_initialize(0, spd_addrmap); + if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */ + sdram_initialize(BOOT_PATH_RESET, spd_addrmap); + else + sdram_initialize(BOOT_PATH_NORMAL, spd_addrmap); printk(BIOS_DEBUG, "Memory initialized\n"); post_code(0x31); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index a45b4da081d2..69880580c106 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -569,6 +569,8 @@ static void sdram_detect_ram_speed(struct sysinfo *s) PRINTK_DEBUG("Drive Memory at %dMHz with CAS = %d clocks\n", ddr_reg_to_mhz(s->selected_timings.mem_clock), s->selected_timings.CAS); // Set memory frequency + if (s->boot_path == BOOT_PATH_RESET) + return; MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x1; reg32 = (MCHBAR32(0xc00) & (~0x70)) | (1 << 10); if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { @@ -676,7 +678,8 @@ static void sdram_clkmode(struct sysinfo *s) reg8 = 1; reg16 = (1 << 8) | (1 << 5); } - MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16; + if (s->boot_path != BOOT_PATH_RESET) + MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16; MCHBAR32(0x220) = 0x58001117; MCHBAR32(0x248) = (MCHBAR32(0x248) | (1 << 23)); @@ -2540,12 +2543,14 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) { struct sysinfo si; u8 reg8; + const char *boot_str[] = { "Normal", "Reset", "Resume"}; PRINTK_DEBUG("Setting up RAM controller.\n"); memset(&si, 0, sizeof(si)); si.boot_path = boot_path; + printk(BIOS_DEBUG, "Boot path: %s\n", boot_str[boot_path]); si.spd_map[0] = spd_addresses[0]; si.spd_map[1] = spd_addresses[1]; si.spd_map[2] = spd_addresses[2]; @@ -2578,18 +2583,25 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) sdram_timings(&si); PRINTK_DEBUG("Done timings (dqs dll enabled)\n"); - sdram_dlltiming(&si); - PRINTK_DEBUG("Done dlltiming\n"); + if (si.boot_path != BOOT_PATH_RESET) { + sdram_dlltiming(&si); + PRINTK_DEBUG("Done dlltiming\n"); + } hpet_udelay(200000); - sdram_rcomp(&si); - PRINTK_DEBUG("Done RCOMP\n"); + if (si.boot_path != BOOT_PATH_RESET) { + sdram_rcomp(&si); + PRINTK_DEBUG("Done RCOMP\n"); + } sdram_odt(&si); PRINTK_DEBUG("Done odt\n"); - while ((MCHBAR8(0x130) & 0x1) != 0); + if (si.boot_path != BOOT_PATH_RESET) { + while ((MCHBAR8(0x130) & 0x1) != 0) + ; + } sdram_mmap(&si); PRINTK_DEBUG("Done mmap\n"); |