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| author | Jeffy Chen <jeffy.chen@rock-chips.com> | 2017-03-03 18:24:02 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-04-28 06:49:18 +0200 |
| commit | 3d966255a446c2a0da108b55b33d163fe4d0020f (patch) | |
| tree | 4c34efcf7772a933dee67a017cf1896bfa31c453 | |
| parent | b0b5987311793c8f9a7d62c8965063c609449032 (diff) | |
| download | coreboot-3d966255a446c2a0da108b55b33d163fe4d0020f.tar.gz coreboot-3d966255a446c2a0da108b55b33d163fe4d0020f.tar.bz2 coreboot-3d966255a446c2a0da108b55b33d163fe4d0020f.zip | |
google/gru: tpm on bob: cr50: add irq clear/irq status for tpm irq
BUG=b:35647967
TEST=boot from bob
Change-Id: I756513f02ac13e159d5b8b1ac2346fa42cf3c219
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf18ed7b8fdf11594f812e5c48a2bd0fde5cb820
Original-Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/452286
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19434
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/google/gru/board.h | 1 | ||||
| -rw-r--r-- | src/mainboard/google/gru/bootblock.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/gru/chromeos.c | 11 |
3 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index 7880cca70d89..8acbe34c9266 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -28,6 +28,7 @@ #define GPIO_P15V_EN GPIO(0, B, 2) #define GPIO_P30V_EN GPIO(0, B, 4) #define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2) +#define GPIO_TPM_IRQ GPIO(0, A, 5) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index d76ec8baf804..4320fcedad24 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -100,6 +100,8 @@ static void configure_tpm(void) rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz); write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0); + + gpio_input_irq(GPIO_TPM_IRQ, IRQ_TYPE_EDGE_RISING); } else { gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull-up */ gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull-up */ diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index d9e5e28f0045..b28e9fc734b3 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -17,6 +17,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <tpm.h> #include "board.h" @@ -35,6 +36,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"}, {GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, +#if IS_ENABLED(CONFIG_GRU_HAS_TPM2) + {GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"}, +#endif }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); @@ -46,3 +50,10 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_EC_IN_RW); gpio_input_pullup(GPIO_EC_IRQ); } + +#if IS_ENABLED(CONFIG_GRU_HAS_TPM2) +int tis_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_TPM_IRQ); +} +#endif |